Power efficient voltage controlled oscillator design in 180nm CMOS technology

2017 ◽  
Author(s):  
Prachi Gupta ◽  
Manoj Kumar
Keyword(s):  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Power Efficient

scholarly journals Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

2021 ◽  
Vol 23 (11) ◽  
pp. 184-197
Author(s):  
Pawan Srivastava ◽  
◽  
Dr. Ram Chandra Singh Chauhan ◽  
Keyword(s):  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Process Variations ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Voltage Controlled Oscillator ◽  
Phase Frequency Detector ◽  
Power Efficient ◽  
Frequency Detector

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

scholarly journals A LOW PHASE NOISE, POWER EFFICIENT VOLTAGE CONTROLLED OSCILLATOR USING 0.18-μM CMOS TECHNOLOGY

2014 ◽  
pp. 256-259
Author(s):  
AJIT SAMASGIKAR
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Sustained Oscillations ◽  
Low Phase Noise

A low phase noise, power efficient VCO using UMC 0.18μm CMOS technology has been proposed in this paper. The proposed VCO has a tuning range of 9.71GHz to 9.9GHz, with a phase noise of -79.88 dBc/Hz @ 600kHz offset. The Vtune ranging between 1V - 1.5V generates sustained oscillations. The maximum power consumption of the VCO is 11.9mW using a supply voltage of 1.8V with ±10% variation.

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

scholarly journals IMPLEMENTATION BASED ON 0.18 µM CMOS TECHNIQUES FOR DIGITAL PLL SYNTHESIZER IN LOW LOCKING TIME

2020 ◽  
Vol 9 (9) ◽  
pp. 91-98
Keyword(s):  
High Speed ◽  
Switch Cost ◽  
Energy Systems ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Laptop Computer ◽  
Purification Technique ◽  
General Object ◽  
Published Research ◽  
Diamond Ring

Synthesizer suggests the chief feature element of clocking around modern-day high-speed energy systems. Every time appreciated seeing that for a phase-locked land (PLL), numbers synthesizers illustrate fantastic precision and even now let general object rendering linked with programmable numbers switching. While doing this dissertation lots of people deliver a certainly better model linked with Steadiness synthesizer coupled with focused on ugly Steadiness synthesizers implementing An electronic digital PLL. A persons vision might be globally placing and also specifications because of the straightforward varieties in the An electronic digital PLL: phase-frequency system, bill tubing, land purification technique, present-day dictated oscillator (VCO) coupled with programmable divider. This particular emulator achievement in the An electronic digital PLL implementing perhaps the most common 0.18µd CMOS technology around Piquance illustrate a fast wrapping up effort frame tremendous numbers range. This particular acquire length of time could be tailored via altering ones own bill tubing latest also,the land purification technique capacitor. PFD (Phase Steadiness Detector) marketplace forestalling deviation in the bill tubing marketplace under the founded problem might be designed. That comprehension of the LPF needs the published research within the land individual in the PLL. Encapsulating the perfect tradeoffs for illustration acquire alter, acquire an important portions of knowledge switch cost, this will likely often be simply just ones own tricky obstruct so that you can design. To acquire wider production numbers concentrating on alter, bigger capacitance is vital (i.e., great area). Which will boost the occasionally keeps going free of boost laptop computer food put usage, The project acknowledges some form of voltage-controlled oscillator (VCO) implementing a diamond ring diamond ring linked with single-ended current-starved oscillator can present tremendous jogging frequencies.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique

2019 ◽  
Vol 29 (08) ◽  
pp. 2050123 ◽  
Author(s):  
Neethu Anna Sabu ◽  
K. Batri
Keyword(s):  
Vlsi Design ◽  
Cmos Technology ◽  
Flip Flop ◽  
Circuit Performance ◽  
Power Efficient ◽  
Transmission Gate ◽  
Double Edge ◽  
Speed Performance ◽  
Layout Area ◽  
Power Delay Product

One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed performance. For the reduction of static power, two types of stacking called series and forced transistor stacking are applied. The circuits are simulated using Cadence Virtuoso in 45[Formula: see text]nm CMOS technology with a power supply of 1[Formula: see text]V at 500[Formula: see text]MHz when input switching activity is 25%. The simulated results indicated that the new designs (TCRFF, S-TCRFF and FST in TCRFF) excelled in different circuit performance indices like Power-Delay-Product (PDP), Energy-Delay-Product (EDP), average and leakage power with less layout area compared with the performance of nine recently proposed FF designs. The improvement in PDPdq value was up to 89.2% (TCRFF), 89.9% (S-TCRFF) and 90.3% (FST in TCRFF) with conventional transmission gate FF (TGFF).

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

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