Alternative Compliant Interconnects: Thermo-Mechanical Reliability, Design and Testing

2001 ◽  
Author(s):  
Lunyu Ma ◽  
Qi Zhu ◽  
Suresh Sitaraman
Keyword(s):  
Low Cost ◽  
Fabrication Process ◽  
Design Parameters ◽  
Electronic Packages ◽  
Wafer Level ◽  
Free Standing ◽  
Reliability Design ◽  
Fine Pitch ◽  
Conventional Photolithography ◽  
Design And Testing

Abstract Two types of novel compliant interconnects are being proposed in this paper. The advantages of these two types of compliant interconnects are: accommodation of the mismatch due to different thermal expansions in electronic packages, integration with wafer-level fabrication process, low cost, fine pitch and high I/O density. The first type is a highly-compliant cantilevered spring interconnect for the next generation packaging and probing technology. To understand the reliability of the package with this novel compliant spring interconnect structure and the typical behavior of sliding contact, test vehicles with different orientations of the cantilevered springs (21 μm pitch) have been fabricated, assembled and subjected to thermal cycling test. In-situ resistance and temperature measurements have been conducted. The second type is a compliant free-standing interconnect, One-Turn Helix (OTH) structure. This structure is built as an one-turn strip helix in order to get good compliance in space. It can be fabricated through conventional photolithography-based IC fabrication process. Optimal design parameters have been identified for this structure taking into consideration the thermo-mechanical and electrical behavior of this unique structure.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Thermomechanical Design for Fine Pitch 3D-IC Packages

2012 ◽  
Vol 2012 (1) ◽  
pp. 001001-001009 ◽  
Author(s):  
Akihiro Horibe ◽  
Sayuri Kohara ◽  
Kuniaki Sueoka ◽  
Keiji Matsumoto ◽  
Yasumitsu Orii ◽  
...  
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
High Stress ◽  
High Viscosity ◽  
Thermomechanical Properties ◽  
Design Parameters ◽  
Element Analysis ◽  
Package Design ◽  
Fine Pitch ◽  
Silicon Vias

Low stress package design is one of the greatest challenges for the realization of reliable 3D integrated devices, since they are composed of elements susceptible to failures under high stress such as thin dies, metal through silicon vias (TSVs), and fine pitch interconnections. In variety of package components, an organic interposer is a key to obtain low cost modules with high density I/Os. However, the large mismatch in coefficient of thermal expansion (CTE) between silicon dies and organic laminates causes high stress in an organic package. The major parametric components in 3D devices are dies with /without Cu-TSVs, laminates, bumps, and underfill layers. Especially, the die thicknesses and underfill properties are ones of the parameters that give us some range to control as package design parameters. In general, the underfill material with a high modulus and a low CTE is effective in reducing the stress in solder interconnections between the Si die and the laminate. However, the filler content of underfill materials with such mechanical properties generally results in high viscosity. The use of high viscous materials in between silicon dies in 3D modules can degrade process ability in 3D integration. In this study, we show that the interchip underfills in 3D modules have a wider mechanical property window than in 2D modules even with fine pitch interconnections consisting mostly of intermetallic compounds (IMCs). Also the finite element analysis results show that the optimization of the structural or thermomechanical properties of organic laminates and interchip underfill contributes to reduction of stressing thinned silicon dies which may have some risks to the device performance.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Compliant Stress-Engineered Interconnects for Next-Generation Packaging

2004 ◽  
Author(s):  
Kevin M. Klein ◽  
Suresh K. Sitaraman
Keyword(s):  
Life Stress ◽  
Low Cost ◽  
Intrinsic Stress ◽  
Wafer Level ◽  
Element Analysis ◽  
Operational Conditions ◽  
Technology Roadmap ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Future Demands

Future demands of microelectronic packing include increasing input/output (I/O) densities, providing high frequency capabilities, and maintaining sufficient reliability while keeping costs minimal. Organic materials with Coefficients of Thermal Expansions (CTE) over four times greater than silicon will continue to be used as future substrate materials because of their low cost. Consistent with the International Technology Roadmap for Semiconductors (ITRS, 2003), chip-to-substrate interconnects will need to have a pitch approximately equal to 40μm by the year 2012 and be able to accommodate the silicon and organic CTE mismatch without resorting to expensive reliability solutions. The demand for fine pitch chip-to-substrate interconnects combined with the CTE mismatch, creates significant demands for overall interconnect compliance as means to ensure reliability, through increasing fatigue life. Stress-engineered compliant off-chip interconnects are capable meeting future interconnect demands. Such interconnects are fabricated from stress-engineered metal thin-films using traditional IC fabrication methods and can be integrated with wafer level packing. A systematic design approach has been used to optimize interconnect geometry for use with estimated operational conditions. Finite Element Analysis (FEA) and Regression modeling have been used to create macro-models of interconnect behavior to assist in the optimization of the geometric design. Copper and Copper-Molybdenum are considered as interconnect material and the development intrinsic stress within copper is investigated via sputter deposition.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

300mm Large Scale eWLB(embedded Wafer Level BGA) : Cost Effective Solution with Performance

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001046-001070
Author(s):  
Seung Wook Yoon ◽  
Yaojian Lin ◽  
Pandi C. Marimuthu ◽  
Yeong J. Lee
Keyword(s):  
Large Scale ◽  
Low Cost ◽  
Cost Effective ◽  
Batch Process ◽  
Dielectric Materials ◽  
Design Parameters ◽  
Wafer Level ◽  
Molding Compound ◽  
Package Size ◽  
Chip Size

Demand for Wafer Level Package (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. The increasing demand for new and more advanced electronic products with smaller form factor, superior functionality and performance is driving the integration of functionality into the third dimension. There are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. 200mm eWLB is in HVM from industry last three years and there was need to move 300mm for scaling-up and low-cost solutions. This paper will highlight some of the recent advancements in large scale 300mm eWLB development. Compared to 200mm case, 300mm has more warpage and process issues due to its area increase. Thermo-mechanical simulation shows 100~150% more warpage with 300mm compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper presents study of process optimization for 300mm eWLB and mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps of scalability for higher throughput and manufacturability.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Three-Mask Fabrication and Optimized Design of First-Level Free-Standing Interconnect for Microelectronics Application

2003 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Analytical Models ◽  
Optimized Design ◽  
Wafer Level ◽  
Free Standing ◽  
Mechanical Compliance ◽  
Compliant Interconnect ◽  
Free Solder

Advances in compliant off-chip interconnects have achieved great strides. G-Helix, an electroplated compliant chip-to-substrate interconnect has the potential for accomplishing low-cost, easy-to-fabricate, wafer-level packaging. In this work, the design, fabrication, optimization and reliability of the G-Helix compliant off-chip interconnects have been studied. A three-mask process was used to successfully fabricate the free-standing G-Helix compliant interconnect. The mechanical compliance and the electrical parasitics were studied through numerical and analytical models. Response Surface Methodology (RSM) was used to maximize the mechanical compliance and minimize the electrical parasitics as well as the stresses induced in the interconnect. It is also seen through the models that an array of interconnects will be able to withstand the die and the heat-sink weight without plastically yielding. Also, the G-Helix interconnect assembly on organic printed circuit board using lead-free solder will be able to withstand more than 1000 accelerated thermal cycles without the need for an underfill.

IoT based e-Healthcare System to Enable Remote Patient Care based on Cloud Server

2017 ◽  
Vol 7 (7) ◽  
pp. 36
Author(s):  
P.Venu Gopala Rao ◽  
Eslavath Raja ◽  
Ramakrishna Gandi ◽  
G. Ravi Kumar
Keyword(s):  
Low Cost ◽  
Vital Signs ◽  
Smart Phone ◽  
Medical Professional ◽  
Design Parameters ◽  
Cloud Server ◽  
Significant Area ◽  
Efficient Data ◽  
System Data ◽  
Remote Patient

IoT (Internet of Things) has become most significant area of research to design an efficient data enabled services with the help of sensors. In this paper, a low-cost system design for e-healthcare service to process the sensitive health data is presented. Vital signs of the human body are measured from the patient location and shared with a registered medical professional for consultation. Temperature and heart rate are the major signals obtained from a patient for the initial build of the system. Data is sent to a cloud server where processing and analysis is provided for the medical professional to analyze. Secure transmission and dissemination of data through the cloud server is provided with an authentication system and the patient could be able to track his data through a smart phone on connecting to the cloud server. A prototype of the system along with its design parameters has been discussed.

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