Microwave Module Thermal Considerations for Future Higher Powered MMICs in Phased Array Radars

2003 ◽  
Author(s):  
James S. Wilson
Keyword(s):  
Thermal Management ◽  
Temperature Difference ◽  
Integrated Circuit ◽  
Heat Dissipation ◽  
Phased Array ◽  
Waste Heat ◽  
Heat Removal ◽  
Thermal Design ◽  
Rf Power ◽  
Phased Array Radar

Advances in RF power generation capability at the device level will soon force a change in phased array radar thermal management. The efficiency in converting electrical power into transmitted power is not increasing as rapidly which means that higher RF power generating devices also dissipate more heat. Removing this waste heat creates several thermal challenges including the topic of this paper, namely thermal issues at the die and package level. A comparison of the temperature differences between the junction and ambient shows that even at present heat dissipation levels, the temperature difference at the integrated circuit level is already a significant fraction of the total rise. Further increases in the device level heat dissipation will increase the temperature difference at the integrated circuit level to nearly unmanageable levels unless device-level design changes are made. Maintaining acceptable junction temperature levels will require lower device mounting surface temperatures or some thermally better method of die attachment and heat removal. Dividing the thermal management of a phased array radar into two portions (integrated circuit level and everything else) reveals that while thermal improvements at the system and packaging level are useful for near-future radar designs, thermal design and management at the device and package levels are crucial.

Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal

2016 ◽  
Vol 138 (1) ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Three Dimensional ◽  
Heat Removal ◽  
Back Side

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active integrated circuit (IC) area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29 kW/cm3, respectively.

Robust Thermal Management for Embedded CPU and GPUs in Displays

2011 ◽  
Author(s):  
Sung Ki Kim ◽  
Woo Young Kan ◽  
Sang Hak Kim ◽  
Vincent Tan ◽  
Gamal Refai-Ahmed ◽  
...  
Keyword(s):  
Thermal Management ◽  
Heat Dissipation ◽  
Form Factors ◽  
Thermal Design ◽  
Flat Panel Display ◽  
Large Format ◽  
Digital Signage ◽  
Operation Conditions ◽  
Signage System ◽  
Embedded Computing System

Digital signage systems are large format displays that are typically installed in public areas for advertisement and informative publications. This emerging technology is considered as a major category in the large format display market. In general, a digital signage system consists of a flat panel display consisting of high brightness screen and operation circuits. Also, special features of high performance embedded computing system exist in very small form factors. Such products, however, are accompanied with high heat dissipation of the internal components and are usually exposed to very harsh environments for more frequent exposure to customers. Also the installation schemes of the products vary for different objectives, and a robust thermal design is required to guarantee the system reliability considering corner scenarios within the design space. The objective of the present study is to investigate the effect of installation environment on the thermal performance of a display assembly resembling a digital signage system. Design criteria for a proper thermal management scheme are proposed. The thermal characteristics of a digital signage system are presented in various operation conditions and each thermal design parameter is discussed thoroughly to ensure the reliability requirements of the digital signage system are met.

Cloud Computing Applied for Numerical Study of Thermal Characteristics of SIP

2013 ◽  
pp. 166-175
Author(s):  
S. K. Maharana ◽  
Praveen B. Mali ◽  
Ganesh Prabhakar ◽  
Sunil J ◽  
Vignesh Kumar
Keyword(s):  
Cloud Computing ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Heat Dissipation ◽  
Numerical Study ◽  
Control Volume ◽  
Thermal Characteristics ◽  
Thermal Dissipation ◽  
Volume Method ◽  
Power And Energy

Thermal management of integrated circuit (IC) and system-in-package (SIP) has gained importance as the power density and requirement for IC design have increased and need exists to analyse the heat dissipation performance characteristics of IC under use. In this paper, the authors examine the thermal characteristics of materials of IC. The authors leverage Cloud Computing architecture to remotely compute the dissipation performance parameters. Understanding thermal dissipation performance, which explains the thermal management of IC, is important for chip performance, as well as power and energy consumption in a chip or SIP. Using architectural understanding of Software as a Service (SaaS), the authors develop an efficient, fast, and secure simulation technique by leveraging control volume method (CVM) of linearization of relevant equations. Three chips are kept in tandem to make it a multi-chip module (MCM) to realise it as a smaller and lighter package. The findings of the study are presented for different dimensions of chips inside the package.

Compact Transient Thermal Model of Microfluidically Cooled Three-Dimensional Stacked Chips With Pin-Fin Enhanced Microgap

2021 ◽  
Vol 143 (3) ◽  
Author(s):  
Yuanchen Hu ◽  
Md Obaidul Hossen ◽  
Zhimin Wan ◽  
Muhannad S. Bakir ◽  
Yogendra Joshi
Keyword(s):  
Heat Transfer ◽  
Integrated Circuit ◽  
High Performance ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
Power Estimation ◽  
Leakage Power ◽  
Pin Fin ◽  
Pin Fins

Abstract Three-dimensional (3D) stacked integrated circuit (SIC) chips are one of the most promising technologies to achieve compact, high-performance, and energy-efficient architectures. However, they face a heat dissipation bottleneck due to the increased volumetric heat generation and reduced surface area. Previous work demonstrated that pin-fin enhanced microgap cooling, which provides fluidic cooling between layers could potentially address the heat dissipation challenge. In this paper, a compact multitier pin-fin single-phase liquid cooling model has been established for both steady-state and transient conditions. The model considers heat transfer between layers via pin-fins, as well as the convective heat removal in each tier. Spatially and temporally varying heat flux distribution, or power map, in each tier can be modeled. The cooling fluid can have different pumping power and directions for each tier. The model predictions are compared with detailed simulations using computational fluid dynamics/heat transfer (CFD/HT). The compact model is found to run 120–600 times faster than the CFD/HT model, while providing acceptable accuracy. Actual leakage power estimation is performed in this codesign model, which is an important contribution for codesign of 3D-SICs. For the simulated cases, temperatures could decrease 3% when leakage power estimation is adopted. This model could be used as electrical-thermal codesign tool to optimize thermal management and reduce leakage power.

scholarly journals Integrated microchannel cooling in a three dimensional integrated circuit: A thermal management

2016 ◽  
Vol 20 (3) ◽  
pp. 899-902
Author(s):  
Kang-Jia Wang ◽  
Zhong-Liang Pan
Keyword(s):  
Thermal Management ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Design Guidelines ◽  
Thermal Design ◽  
Steady State Temperature ◽  
Detailed Evaluation ◽  
Microchannel Cooling ◽  
Three Dimensional Integrated Circuit ◽  
The Relationship

Microchannel cooling is a promising technology for solving the three-dimensional integrated circuit thermal problems. However, the relationship between the microchannel cooling parameters and thermal behavior of the three dimensional integrated circuit is complex and difficult to understand. In this paper, we perform a detailed evaluation of the influence of the microchannel structure and the parameters of the cooling liquid on steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for three dimensional integrated circuit with microchannel cooling.

Benchmarking Study on the Thermal Management Landscape for 3D ICs: From Back-Side to Volumetric Heat Removal

2015 ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Thermal Management ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Heat Removal ◽  
Back Side ◽  
Cooling Channels ◽  
Fluid Delivery ◽  
Single Side

An overview of the thermal management landscape with focus on heat dissipation from 3D chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side and, finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely, 1) dual-side cooling, implemented by a thermally active interposer, 2) interlayer cooling with 4-port fluid delivery and drainage at 100 kPa pressure drop, and 3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence, enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low TSV heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active IC area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29kW/cm3, respectively.

scholarly journals Thermal management of the hotspots in 3-D integrated circuits

2018 ◽  
Vol 22 (4) ◽  
pp. 1685-1690 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Cui-Ling Li ◽  
Guo-Dong Wang ◽  
Hong-Wei Zhu
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Vertical Integration ◽  
Integrated Circuit ◽  
Design Guidelines ◽  
Thermal Design ◽  
Micro Channel ◽  
Through Silicon Vias ◽  
Microchannel Cooling ◽  
Silicon Vias

Vertical integration for microelectronics possesses significant challenges due to its fast dissipation of heat generated in multiple device planes. This paper focuses on thermal management of a 3-D integrated circuit, and micro-channel cooling is adopted to deal with the 3-D integrated circuitthermal problems. In addition, thermal through-silicon vias are also used to improve the capacity of heat trans-mission. It is found that combination of microchannel cooling and thermal through-silicon vias can remarkably alleviate the hotspots. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3-D integrated circuits.

scholarly journals Structure Optimization of Battery Thermal Management Systems Using Sensitivity Analysis and Stud Genetic Algorithms

2021 ◽  
Vol 11 (16) ◽  
pp. 7440
Author(s):  
Jiahui Chen ◽  
Dongji Xuan ◽  
Biao Wang ◽  
Rui Jiang
Keyword(s):  
Genetic Algorithm ◽  
Sensitivity Analysis ◽  
Thermal Management ◽  
Temperature Difference ◽  
Flow Resistance ◽  
Heat Dissipation ◽  
Structural Parameters ◽  
Battery Pack ◽  
Management Systems ◽  
Battery Thermal Management

Battery thermal management systems (BTMS) are hugely important in enhancing the lifecycle of batteries and promoting the development of electric vehicles. The cooling effect of BTMS can be improved by optimizing its structural parameters. In this paper, flow resistance and heat dissipation models were used to optimize the structure of BTMS, which were more efficient than the computational fluid dynamics method. Subsequently, five structural parameters that affect the temperature inside the battery pack were analyzed using single-factor sensitivity analysis under different inlet airflow rates, and three structural parameters were selected as the constraints of a stud genetic algorithm. In this stud genetic algorithm, the maximal temperature difference obtained by the heat dissipation model was within 5K as the constraint function, where the objective function minimized the overall area of the battery pack. The BTMS optimized by the stud genetic algorithm was reduced by 16% in the maximal temperature difference and saved 6% of the battery package area compared with the original BTMS. It can be concluded that the stud genetic algorithm combined with the flow resistance network and heat dissipation models can quickly and efficiently optimize the air-cooled BTMS to improve the cooling performance.

Cloud Computing Applied for Numerical Study of Thermal Characteristics of SIP

2011 ◽  
Vol 1 (3) ◽  
pp. 12-21
Author(s):  
S. K. Maharana ◽  
Praveen B. Mali ◽  
Ganesh Prabhakar ◽  
Sunil J ◽  
Vignesh Kumar
Keyword(s):  
Cloud Computing ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Heat Dissipation ◽  
Numerical Study ◽  
Control Volume ◽  
Thermal Characteristics ◽  
Thermal Dissipation ◽  
Volume Method ◽  
Power And Energy

Thermal management of integrated circuit (IC) and system-in-package (SIP) has gained importance as the power density and requirement for IC design have increased and need exists to analyse the heat dissipation performance characteristics of IC under use. In this paper, the authors examine the thermal characteristics of materials of IC. The authors leverage Cloud Computing architecture to remotely compute the dissipation performance parameters. Understanding thermal dissipation performance, which explains the thermal management of IC, is important for chip performance, as well as power and energy consumption in a chip or SIP. Using architectural understanding of Software as a Service (SaaS), the authors develop an efficient, fast, and secure simulation technique by leveraging control volume method (CVM) of linearization of relevant equations. Three chips are kept in tandem to make it a multi-chip module (MCM) to realise it as a smaller and lighter package. The findings of the study are presented for different dimensions of chips inside the package.

Major Considerations in System-Level Thermal Design of Next-Generation Telecommunications Equipment

2009 ◽  
Author(s):  
Lang Yuan ◽  
Jignesh Patel
Keyword(s):  
Thermal Management ◽  
Heat Dissipation ◽  
Acoustic Noise ◽  
Field Tests ◽  
Thermal Design ◽  
System Level ◽  
Next Generation ◽  
Air Filter ◽  
Planning Stage ◽  
The Impact

The thermal management of next-generation telecommunications equipment is becoming more challenging than ever before, thanks to the elevated ambient temperature requirements (up to 65°C) from network carriers, and the thermal limitation of critical components such as optical transceivers (with a max. rating of 85°C). With thousands of watts of heat dissipation from a single shelf, a systematic methodology has to be developed at the planning stage so that every possible means to streamline the thermal management can be integrated into the system-level design. This paper uses a next-generation fiber-optic telecom product as an example to demonstrate the impact of some major mechanical/electrical parameters (such as fan curve, acoustic noise, air filter, copper content of PCB and baffles, etc.) on the thermal performance of the system. Each factor is quantitatively analyzed based on field tests, and good design practices are suggested.

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