IMPLEMENTING LOW-COST FAULT TOLERANCE VIA HYBRID SYNCHRONOUS/ASYNCHRONOUS CHECKS

2013 ◽  
Vol 22 (07) ◽  
pp. 1350058 ◽  
Author(s):  
JIANLI LI ◽  
QINGPING TAN ◽  
LANFANG TAN
Keyword(s):  
Low Cost ◽  
Fault Coverage ◽  
Commodity Market ◽  
Transient Faults ◽  
Time Analysis ◽  
Scale Down ◽  
Check Method ◽  
Benchmark Suite ◽  
Superscalar Pipeline ◽  
Minimal Hardware

As semiconductor technologies scale down to deep sub-micron dimensions, transient faults will soon become a critical reliability concern. Due to their prohibitive costs, traditional high-end solutions are unacceptable for the mainstream commodity market. This paper presents FTPIPE, a hybrid software/hardware solution, which provides sufficient fault coverage with affordable overhead for single-threaded programs running on commodity systems. Leveraging existing exception mechanisms with minor modifications to handle exception-causing faults, FTPIPE focuses on tolerating silent data corruptions by using compile-time analysis and performing selective instruction replication in a modern superscalar pipeline extended with minimal hardware overhead. Unlike existing instruction replication-based solutions, which detect faults by synchronous checks, the FTPIPE platform has exploited a novel hybrid synchronous/asynchronous check method for the replicated instructions. In this manner, better performance can be obtained without degradation of fault coverage. By synchronous checks, the validation of the result of a replicated instruction must be finished before it is committed, whereas such a guarantee is not required by an asynchronous check. Evaluation using a set of nine programs from the Mibench benchmark suite demonstrates that FTPIPE can tolerate 89.8% of transient faults under a modest performance overhead of 20.1%.

scholarly journals SOFTWARE IMPLEMENTED HARDWARE-TRANSIENT FAULTS DETECTION

2014 ◽  
pp. 26-30
Author(s):  
Goutam Kumar Saha
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Low Cost ◽  
Transient Faults ◽  
Fault Tolerant System ◽  
Cost Approach ◽  
Run Time ◽  
Commodity Systems ◽  
Fail Safe ◽  
Register Error

This paper examines a software implemented self-checking technique that is capable of detecting processorregisters' hardware-transient faults. The proposed approach is intended to detect run-time transient bit-errors in memory and processor status register. Error correction is not considered here. However, this low-cost approach is intended to be adopted in commodity systems that use ordinary off-the-shelf microprocessors, for the purpose of operational faults detection towards gaining fail-safe kind of fault tolerant system.

scholarly journals A Prototype Photoplethysmography Electronic Device that Distinguishes Congestive Heart Failure from Healthy Individuals by Applying Natural Time Analysis

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1288 ◽  
Author(s):  
George Baldoumas ◽  
Dimitrios Peschos ◽  
Giorgos Tatsis ◽  
Spyridon K. Chronopoulos ◽  
Vasilis Christofilakis ◽  
...  
Keyword(s):  
Heart Failure ◽  
Congestive Heart Failure ◽  
Electronic Device ◽  
Low Cost ◽  
Prototype System ◽  
Healthy Individuals ◽  
Time Analysis ◽  
Clear Separation ◽  
Natural Time ◽  
Natural Time Analysis

In this paper, a prototype photoplethysmography (PPG) electronic device is presented for the distinction of individuals with congestive heart failure (CHF) from the healthy (H) by applying the concept of Natural Time Analysis (NTA). Data were collected simultaneously with a conventional three-electrode electrocardiography (ECG) system and our prototype PPG electronic device from H and CHF volunteers at the 2nd Department of Cardiology, Medical School of Ioannina, Greece. Statistical analysis of the results show a clear separation of CHF from H subjects by means of NTA for both the conventional ECG system and our PPG prototype system, with a clearly better distinction for the second one which additionally inherits the advantages of a low-cost portable device.

scholarly journals Sediment Bed Borehole Advection Method

Water ◽  
2020 ◽  
Vol 12 (12) ◽  
pp. 3380
Author(s):  
Scott Augustine ◽  
Jaehyun Cho ◽  
Harald Klammler ◽  
Kirk Hatfield ◽  
Michael D. Annable
Keyword(s):  
Time Series Data ◽  
Low Cost ◽  
Vertical Direction ◽  
Series Data ◽  
Time Analysis ◽  
Sediment Bed ◽  
Concentration Time Series ◽  
Flux Measurements ◽  
Darcy Flux ◽  
Sediment Interface

This paper introduces and tests the Sediment Bed Borehole Advection Method (SBBAM), a low cost, point-measurement technique which utilizes a push-point probe to quantify the vertical direction and magnitude of Darcy flux at the surface water—groundwater sediment interface. The Darcy flux measurements are derived from the residence-time analysis of tracer arrival calculated from measured tracer concentration time-series data. The technique was evaluated in the laboratory using a sediment bed simulator tank at eight flow rates (1–90 cm/day). Triplicate test runs for each flow rate returned average errors between 4–20 percent; r2 = 0.9977.

scholarly journals Characteristic Fingerprint Based on Low Polar Constituents for Discrimination ofWolfiporia extensaaccording to Geographical Origin Using UV Spectroscopy and Chemometrics Methods

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Yan Li ◽  
Ji Zhang ◽  
Yanli Zhao ◽  
Zhimin Li ◽  
Tao Li ◽  
...  
Keyword(s):  
Geographical Origin ◽  
Uv Spectroscopy ◽  
Low Cost ◽  
Hierarchical Cluster ◽  
Asian Countries ◽  
Time Analysis ◽  
Pattern Recognition Methods ◽  
History Of ◽  
Medicinal Fungi ◽  
Short Time

The fungus speciesWolfiporia extensahas a long history of medicinal usage and has also been commercially used to formulate nutraceuticals and functional foods in certain Asian countries. In the present study, a practical and promising method has been developed to discriminate the dried sclerotium ofW. extensacollected from different geographical sites based on UV spectroscopy together with chemometrics methods. Characteristic fingerprint of low polar constituents of sample extracts that originated from chloroform has been obtained in the interval 250–400 nm. Chemometric pattern recognition methods such as partial least squares discriminant analysis (PLS-DA) and hierarchical cluster analysis (HCA) were applied to enhance the authenticity of discrimination of the specimens. The results showed thatW. extensasamples were well classified according to their geographical origins. The proposed method can fully utilize diversified fingerprint characteristics of sclerotium ofW. extensaand requires low-cost equipment and short-time analysis in comparison with other techniques. Meanwhile, this simple and efficient method may serve as a basis for the authentication of other medicinal fungi.

scholarly journals An SVM-Based NAND Flash Endurance Prediction Method

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 746
Author(s):  
Haichun Zhang ◽  
Jie Wang ◽  
Zhuo Chen ◽  
Yuqian Pan ◽  
Zhaojun Lu ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Low Cost ◽  
Prediction Method ◽  
Machine Learning Algorithms ◽  
Nand Flash ◽  
Transient Faults ◽  
Nand Flash Memory ◽  
Process Improvements ◽  
Noise Interference

NAND flash memory is widely used in communications, commercial servers, and cloud storage devices with a series of advantages such as high density, low cost, high speed, anti-magnetic, and anti-vibration. However, the reliability is increasingly getting worse while process improvements and technological advancements have brought higher storage densities to NAND flash memory. The degradation of reliability not only reduces the lifetime of the NAND flash memory but also causes the devices to be replaced prematurely based on the nominal value far below the minimum actual value, resulting in a great waste of lifetime. Using machine learning algorithms to accurately predict endurance levels can optimize wear-leveling strategies and warn bad memory blocks, which is of great significance for effectively extending the lifetime of NAND flash memory devices and avoiding serious losses caused by sudden failures. In this work, a multi-class endurance prediction scheme based on the SVM algorithm is proposed, which can predict the remaining P-E cycle level and the raw bit error level after various P-E cycles. Feature analysis based on endurance data is used to determine the basic elements of the model. Based on the error features, we present a variety of targeted optimization strategies, such as extracting the numerical features closely related to the endurance, and reducing the noise interference of transient faults through short-term repeated operations. Besides a high-parallel flash test platform supporting multiple protocols, a feature preprocessing module is constructed based on the ZYNQ-7030 chip. The pipelined module of SVM decision model can complete a single prediction within 37 us.

scholarly journals PBench: A Parallel, Real-Time Benchmark Suite

2018 ◽  
Vol 1 (1) ◽  
pp. 178-186 ◽  
Author(s):  
Sevil Serttaş ◽  
Veysel Harun Şahin
Keyword(s):  
Real Time ◽  
Execution Time ◽  
Matrix Multiplication ◽  
Multiprocessor Systems ◽  
Time Analysis ◽  
Worst Case ◽  
Analysis Methods ◽  
Worst Case Execution Time ◽  
Benchmark Suite ◽  
Time Systems

Real-time systems are widely used from the automotive industry to the aerospace industry. The scientists, researchers, and engineers who develop real-time platforms, worst-case execution time analysis methods and tools need to compare their solutions to alternatives. For this purpose, they use benchmark applications. Today many of our computing systems are multicore and/or multiprocessor systems. Therefore, to be able to compare the effectiveness of real-time platforms, worst-case execution time analysis methods and tools, the research community need multi-threaded benchmark applications which scale on multicore and/or multiprocessor systems. In this paper, we present the first version of PBench, a parallel, real-time benchmark suite. PBench includes different types of multi-threaded applications which implement various algorithms from searching to sorting, matrix multiplication to probability distribution calculation. In addition, PBench provides single-threaded versions of all programs to allow side by side comparisons.

Wafer Thinning for Advanced Packaging Applications

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-26
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Scott Kroeger
Keyword(s):  
Low Cost ◽  
High Volume ◽  
Alternative Methods ◽  
Critical Element ◽  
Wafer Level ◽  
Temporary Bonding ◽  
Scale Down ◽  
Advanced Packaging ◽  
Wafer Thinning ◽  
Etch Profile

Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. The high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry. Lower-cost advanced packaging concepts have been developed and are now in high-volume production. Recently, alternative methods for exploiting the z-direction have turned to variations of Fan-Out Wafer Level Packaging (FOWLP), which do not include TSVs. In many of these concepts there is a need to thin the wafer to remove all of the silicon while being selective and not etching a variety of other films that include oxides, nitrides, and metals. In addition, there can be temporary bonding adhesives and mold compounds encapsulating the chips; these must remain undamaged. Another critical element of a successful process is the ability to control the profile of the silicon etch to provide uniform removal. The single wafer wet etching techniques and advanced process control developed for TSV Reveal are applicable to these structures and provide a low-cost alternative to CMP and Plasma processes. To successfully execute the process, several characteristics must be met: the silicon overburden depth and profile need to be determined, the overburden thinning etch needs a fast sculpting etchant, and the finishing etchant needs to be selective to materials that will be exposed at the completion of the etch. In addition, the tool used to perform this sequence needs to have the correct metrology capability, along with properly chosen etchants. Similarly, it is not sufficient to know the required etch profile, the software must be able to execute a unique etch profile for each wafer. In this fashion, the finishing etch time can be kept to a minimum. This is important, as many of the selective etchants have a slow etch rate, and adhesives used do not always hold up to exposure to the chemistries involved for long periods. This paper discusses the use of wet etch wafer thinning processes for new FOWLP applications.

Surface and Structural Properties of TiO2 Nanotubes Formation via Electrochemical Anodization

2013 ◽  
Vol 686 ◽  
pp. 71-76
Author(s):  
Nur Aimi Jani ◽  
Mohd Faizal Achoi ◽  
Mohd Muzamir Mahat ◽  
Saifollah Abdullah ◽  
Zainovia Lockman ◽  
...  
Keyword(s):  
Tio2 Nanotubes ◽  
Low Cost ◽  
Average Diameter ◽  
Electrochemical Anodization ◽  
Electrochemical System ◽  
Time Analysis ◽  
Cross Sectional ◽  
Self Organized ◽  
Current Flows ◽  
Tio2 Nts

An electrochemical anodization is a simple and low cost technique, to electrochemically synthesize self-organized titanium dioxide (TiO2) nanotubes (NTs) from 1M Na2SO4 electrolyte with anodization of Ti foil. The FESEM results showed that the average diameter size and length of TiO2 NTs was found between 50 to 60 nm and 2.5 μm, respectively. The surface morphology of arrays TiO2 NTs is uniformly deposited on Ti substrate. While, the cross-sectional of TiO2 NTs revealed that, the TiO2 NTs is arrays alignment and close each other deposited. From current-anodisation time analysis (I-t) indicates that TiO2 nanotubes were start formed at anodisation time 429.03 sec with current flows is 51.69 mA in electrochemical system.

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