Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu IC’s

2006 ◽  
Author(s):  
Karan Kacker ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Dielectric Material ◽  
Semiconductor Industry ◽  
Cost Effective ◽  
Organic Substrate ◽  
Integrative Approach ◽  
Wafer Level ◽  
Technology Roadmap ◽  
Cte Mismatch ◽  
Compliant Interconnect ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnect are less likely to crack or delaminate the low-K dielectric material in current and future ICs. The interconnects are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we present an integrative approach which uses interconnects with varying compliance and thus varying electrical preformance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermo-mechanical reliability concerns. We also discuss the reliability assessment results of helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects

2013 ◽  
Vol 135 (3) ◽  
Author(s):  
Raphael Okereke ◽  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Cost Effective ◽  
Wafer Level ◽  
Mechanical Compliance ◽  
Interconnect Design ◽  
Compliant Interconnect ◽  
Thermomechanical Reliability ◽  
Interconnect Technology ◽  
Low K ◽  
Level Process

This paper presents a study on a dual-path compliant interconnect design which attempts to improve the balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Implementation of this interconnect technology can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermomechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermomechanical reliability of a dual-path compliant interconnect.

Journey Toward Process Convergence in TSV Technology

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001282-001321
Author(s):  
Sesh Ramaswami ◽  
John Dukovic
Keyword(s):  
Process Integration ◽  
Semiconductor Industry ◽  
Rapid Development ◽  
Chemical Mechanical Planarization ◽  
Cost Effective ◽  
Superior Performance ◽  
Wafer Level ◽  
Unit Process ◽  
Integration Schemes ◽  
Process Convergence

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP). Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products. This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.

Development of G-Helix Structure as Off-Chip Interconnect

2004 ◽  
Vol 126 (2) ◽  
pp. 237-246 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
Mechanical Performance ◽  
Coefficient Of Thermal Expansion ◽  
Mechanical Analysis ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Package Weight ◽  
Mechanical Compliance ◽  
Cte Mismatch

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.

A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

Compliant Stress-Engineered Interconnects for Next-Generation Packaging

2004 ◽  
Author(s):  
Kevin M. Klein ◽  
Suresh K. Sitaraman
Keyword(s):  
Life Stress ◽  
Low Cost ◽  
Intrinsic Stress ◽  
Wafer Level ◽  
Element Analysis ◽  
Operational Conditions ◽  
Technology Roadmap ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Future Demands

Future demands of microelectronic packing include increasing input/output (I/O) densities, providing high frequency capabilities, and maintaining sufficient reliability while keeping costs minimal. Organic materials with Coefficients of Thermal Expansions (CTE) over four times greater than silicon will continue to be used as future substrate materials because of their low cost. Consistent with the International Technology Roadmap for Semiconductors (ITRS, 2003), chip-to-substrate interconnects will need to have a pitch approximately equal to 40μm by the year 2012 and be able to accommodate the silicon and organic CTE mismatch without resorting to expensive reliability solutions. The demand for fine pitch chip-to-substrate interconnects combined with the CTE mismatch, creates significant demands for overall interconnect compliance as means to ensure reliability, through increasing fatigue life. Stress-engineered compliant off-chip interconnects are capable meeting future interconnect demands. Such interconnects are fabricated from stress-engineered metal thin-films using traditional IC fabrication methods and can be integrated with wafer level packing. A systematic design approach has been used to optimize interconnect geometry for use with estimated operational conditions. Finite Element Analysis (FEA) and Regression modeling have been used to create macro-models of interconnect behavior to assist in the optimization of the geometric design. Copper and Copper-Molybdenum are considered as interconnect material and the development intrinsic stress within copper is investigated via sputter deposition.

Multi Beam Full Cut Dicing of Thin Si IC Wafers

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001446-001474
Author(s):  
Jeroen van Borkulo ◽  
Richard van der Stam ◽  
Guido Knippels
Keyword(s):  
Dominant Role ◽  
Semiconductor Industry ◽  
Single Step ◽  
Efficient Manner ◽  
Technology Roadmap ◽  
Beam Laser ◽  
3D Packaging ◽  
Cost Efficient ◽  
Low K ◽  
Si Wafer

The ongoing trend to thinner wafers which are needed for continuous miniaturization, 3D packaging and IC performance, inevitably means that sole blade dicing evolution is coming to an end. Over the last years several technologies to handle the separation process of thin Si wafer dicing have been evaluated (DBG, Stealth, Plasma, etc). Although they are capable for certain applications to meet the process specifications, they achieve this at expense of flexibility, productivity and process costs. ALSI, the inventor of multi beam dicing for semiconductor materials, has developed a technology using a multi beam laser concept which allows to dice through thin Si IC wafers while achieving a die strength equal or higher than achieved with blade dicing. In this single step process a multi beam laser configuration allows to remove the (ultra) low-K and metal top structures, dice through the Si substrate and recover the die strength (>450MPa for a 70um Si wafer). This technology allows the semiconductor industry to continue with the development of advanced node wafer technology utilizing (ultra) low-K and thick metal structures while having a separation technology that can cope with all these process steps. The presentation will address how the multi beam laser dicing process is an enabling technology and the first process in the world that can meet the die strength criteria without the need of additional process steps which increase the cost and reduce the flexibility and yield of the process. Multi beam laser dicing allows semiconductor manufacturers to execute their technology roadmap in a cost efficient manner. This presentation will address in depth, the challenges and issue's that semiconductor manufacturers are facing with respect to the dicing of thin (ultra) low-K IC wafers. We will present the die strength and quality that has been achieved using the multi beam dicing technology and compare this to other separation technologies. We will disclose how a multi beam process will play a dominant role in achieving an extremely small Heat Affected Zone combined with a significantly higher productivity. It will be demonstrated how a unique combination and optimization of multiple beams, pulse duration, and low pulse energy, can meet the challenging requirements set by the industry. In addition dicing results and achieved productivities will be presented.

Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 002082-002094
Author(s):  
Pingye Xu ◽  
Michael C. Hamilton
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Process Temperature ◽  
High Yield ◽  
Wafer Level ◽  
Micro Fabrication ◽  
Compliant Interconnect ◽  
Sac Solder

With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly. Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate. In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging. The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.

High Speed Fluorescent Inspection of Non-visible defects

2016 ◽  
Vol 2016 (1) ◽  
pp. 000540-000544
Author(s):  
Gurvinder Singh ◽  
Chet Suresh ◽  
John Thornell ◽  
Woo Young Han
Keyword(s):  
White Light ◽  
High Speed ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Organic Residue ◽  
Wafer Level ◽  
Root Cause ◽  
Fluorescent Microscope ◽  
Advanced Packaging ◽  
Field Reliability

Abstract The semiconductor industry continues to drive down defectivity rates, especially as the liability to ship replacement parts for field failures is pushed back into the supply chain. As dimensions are driven down to finer pitch, there are a certain class of defects that are caused by organic residue. Inspection using white light for advanced packaging is well known. However, organic residue defects appear transparent to white light but can be the root cause of field reliability issues. Residue on top of a bump, as an example, could cause damage to the part when operating at high temperatures in the field. Up until now, such an inspection would have been performed either using a manual fluorescent microscope or not at all. A well understood capability gap in the industry, defects due to organic residue are present in copper pillar bump and wafer level chip scale packages – both fan-in and fan-out, as well as packages based on organic substrate. This paper presents data from high-speed fluorescent inspection that could address this problem in a unique way that was not possible up until now.

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