Improvement of Short Channel Mobility and Operational Stability of Pentacene Bottom-Contact Transistors with a Sulfuric Acid and Hydrogen Peroxide Mixture (SPM) Treatment of Au Electrodes

2006 ◽  
Vol 965 ◽  
Author(s):  
Haruo Kawakami ◽  
Takahiko Maeda ◽  
Hisato Kato
Keyword(s):  
Hydrogen Peroxide ◽  
Sulfuric Acid ◽  
Contact Resistance ◽  
Gate Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Channel Length ◽  
Short Channel ◽  
Bottom Contact

ABSTRACTWe report a reduction in the contact resistance between pentacene and Au source/drain electrodes of organic field effect transistors (OFETs) with bottom-contact structure. By immersing the Au electrodes in a sulfuric acid and hydrogen peroxide mixture (SPM), the injection barrier between the Au electrodes and pentacene was lowered by approximately 0.2 eV and the contact resistance significantly decreased. The fabricated bottom-contact OFETs revealed a field-effect mobility of more than 0.66 cm2/Vs at a channel length ranging from 3 to 30 μm, which is comparable to that of top-contact OFETs with a 50 μm channel length. The transfer characteristics of the OFET with the SPM treatment were stable even after 44days storage in air under room illumination without any passivation. Moreover, the drain current reduction due to threshold voltage (Vth) shift under continuous application of gate voltage quickly recovered toward the original value with unloading of gate voltage.

Sub-threshold-like charge transport in organic field effect transistor: A study on effective channel thickness

2015 ◽  
Vol 29 (28) ◽  
pp. 1550172
Author(s):  
A. K. Kavala ◽  
A. K. Mukherjee
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Thermionic Emission ◽  
Drain Current ◽  
Channel Length ◽  
Hole Injection ◽  
Emission Model ◽  
Short Channel ◽  
Channel Thickness ◽  
Effective Channel

A short channel organic field effect transistors (OFET) based on Pentacene, having channel length in the range of sub-micrometer, has been numerically modelled for low values of drain voltage. The output characteristics show a nonlinear concave increase of drain current for all values of gate voltages. This anomalous current-voltage behavior, which resembles sub-threshold characteristics of silicon FETs, shows a good match with earlier experimental reports on OFET at low drain voltages. The sub-threshold-like characteristics has been interpreted in light of thermionic-emission model because of the presence of hole injection barrier at drain (gold)/Pentacene interface. The associated analysis has facilitated to obtain a significant parameter, effective channel thickness [Formula: see text], for the first time in case of OFETs. It came out to be roughly 4 nm and 8 nm for experimental devices of poly(3-hexylthiophene-2,5-diyl) and Pentacene, respectively, while the numerically modelled device yielded a value of about 60 nm. Increase of [Formula: see text] with transverse gate electric field is also observed. Physical explanation of the observations is also presented.

A One-Micrometer Channel Length α-Si Thin-Film Field-Effect Transistor

1984 ◽  
Vol 33 ◽  
Author(s):  
Z. Yaniv ◽  
G. Hansell ◽  
M. Vijan ◽  
V. Cannella
Keyword(s):  
Thin Film ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Liquid Crystal Displays ◽  
Channel Length ◽  
Large Area ◽  
Short Channel ◽  
Threshold Voltages ◽  
Effect Transistor ◽  
Si Thin Film

ABSTRACTA new method of fabricating short channel α-Si TFTs has been developed. One-micrometer channel length α-Si thin-film field effect transistors have been fabricated and tested. Threshold voltages as low as 1.9V and field-effect mobilities as high as 1 cm 2/V-sec are reported. These devices were fabricated by techniques compatible with the production of large area liquid crystal displays.

50nm Gate-Length Hydrogen Terminated Diamond Field Effect Transistors – Characterization and Inspection of Operation.

2011 ◽  
Vol 1282 ◽  
Author(s):  
David A. J. Moran ◽  
Donald A. MacLaren ◽  
Samuele Porro ◽  
Richard Hill ◽  
Helen McLelland ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Transmission Electron ◽  
Channel Effects ◽  
Physical And Chemical ◽  
Electron Energy Loss

ABSTRACTHydrogen terminated diamond field effect transistors (FET) of 50nm gate length have been fabricated, their DC operation characterised and their physical and chemical structure inspected by Transmission Electron Microscopy (TEM) and Electron Energy Loss Spectroscopy (EELS). DC characterisation of devices demonstrated pinch-off of the source-drain current can be maintained by the 50nm gate under low bias conditions. At larger bias, off-state output conductance increases, demonstrating most likely the onset of short-channel effects at this reduced gate length.

scholarly journals Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs Shaded Conditions

2020 ◽  
Vol 24 (1) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Prabir Saha
Keyword(s):  
Integrated Circuits ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Cmos Technology ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Analytical Models ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects

Nowadays, the endlessly increasing demand for faster and complex integrated circuits (IC) has been fuelled by the scaling of metal-oxide-semiconductor field-effect-transistors (MOSFET) to smaller dimensions. The continued scaling of MOSFETs approaches its physical limits due to short-channel effects (SCE). Double-gate (DG) MOSFET is one of the promising alternatives as it offers better immunity towards SCEs and can be scaled to the shortest channel length. In future, ICs can be designed using DG-CMOS technology for which mathematical models depicting the electrical characteristics of the DG MOSFETs are foremost needed. In this paper, a review on n-type symmetric DG MOSFETs models has been presented based on the analyses of electrostatic potential distribution, threshold voltage, and drain-current models. Mathematical derivations of the device models are described elaborately, and numerical simulations are also carried out to validate the replicability of models.

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