Low Ohmicity Contacts to Mono- and Polycrystalline Silicon

1982 ◽  
Vol 18 ◽  
Author(s):  
H. B. Harrison ◽  
J. S. Williams ◽  
G. K. Reeves
Keyword(s):  
Integrated Circuits ◽  
Contact Resistance ◽  
Polycrystalline Silicon ◽  
Semiconductor Device ◽  
Rapid Development ◽  
Source Regions ◽  
Device Structures ◽  
Device Applications ◽  
Ohmic Contact Formation ◽  
Impurity Profiles

With the continued rapid development of integrated circuits and the evolution towards higher chip component densities brought about by down–scaling of device dimensions, it is useful to assess the limits of performance of presently known device structures using current fabrication technology. The silicon gate field effect transistor is of obvious importance, since at the present limit of decreasing dimensions these devices are expected to give comparable speed and lower powerdelay products than their bipolar counterparts. The rapid developments in fabrication methods such as increases in wafer dimensions coupled with the reduction in device dimensions has led to a reduction in maximum processing temperatures. In particular, this downward trend is incompatible with the necessity to lower contact resistance given appropriate device down–scaling.In this paper we present techniques using ion implantation and tailored impurity profiles that are compatible with low temperature ohmic contact formation. The application of these techniques to mono- and polycrystalline silicon are presented. Our results suggest that these techniques show considerable promise for semiconductor device applications. As a consequence, a production technology that optimizes the contact resistance to both gate-poly and drain and source regions is being investigated and current results will be presented.

Applications of Laser Annealing in IC Fabrication

1982 ◽  
Vol 13 ◽  
Author(s):  
L.D. Hess ◽  
G. Eckhardt ◽  
S.A. Kokorowski ◽  
G.L. Olson ◽  
A. Gupta ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Ohmic Contacts ◽  
Laser Annealing ◽  
Semiconductor Device ◽  
Furnace Annealing ◽  
Device Structures ◽  
Potential Applications ◽  
General Aspects ◽  
Temperature Heating ◽  
Special Time

ABSTRACTLaser annealing is discussed in the context of potential applications in the fabrication of advanced solid state components and integrated circuits. General aspects of the uniquetemporal and spatial heating distributions that can be obtained with laser heating are presented, and selected examples are given which illustrate the advantage of special time/temperature heating cycles in the processing of specific semiconductor device structures. The performance of silicon and Hgcdte diodes, polysilicon resistors, multiple stacked polysilicon/oxide capacitors, Al/Si ohmic contacts and MOS/SOS transistors fabricated using laser annealing is significantly improved relative to devices fabricatedusing conventional furnace annealing.

Defects in β-SiC thin films grown on α-SiC substrates

1988 ◽  
Vol 46 ◽  
pp. 568-569
Author(s):  
Karren L. More
Keyword(s):  
Thin Films ◽  
Semiconductor Device ◽  
Lattice Mismatch ◽  
Chemical Vapor ◽  
Substrate Material ◽  
Growth Interface ◽  
Si Substrates ◽  
Thermal Expansion Coefficients ◽  
Device Applications ◽  
Expansion Coefficients

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

TEM Sample Preparation by Single-Sided Low-Energy Ion Beam Etching

2011 ◽  
Author(s):  
Liew Kaeng Nan ◽  
Lee Meng Lung
Keyword(s):  
Sample Preparation ◽  
Semiconductor Device ◽  
Ion Beam ◽  
Critical Dimension ◽  
Low Energy ◽  
Ex Situ ◽  
Good Image Quality ◽  
Ion Beam Etching ◽  
Device Structures ◽  
Common Technique

Abstract Conventional FIB ex-situ lift-out is the most common technique for TEM sample preparation. However, the scaling of semiconductor device structures poses great challenge to the method since the critical dimension of device becomes smaller than normal TEM sample thickness. In this paper, a technique combining 30 keV FIB milling and 3 keV ion beam etching is introduced to prepare the TEM specimen. It can be used by existing FIBs that are not equipped with low-energy ion beam. By this method, the overlapping pattern can be eliminated while maintaining good image quality.

Effects of Backside Circuit Edit on Transistor Characteristics

2007 ◽  
Author(s):  
R.K. Jain ◽  
T. Malik ◽  
T.R. Lundquist ◽  
Q.S. Wang ◽  
R. Schlangen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Intrinsic Parameters ◽  
Chip Type ◽  
Device Structures ◽  
Before And After ◽  
Silicon Device ◽  
Metal Layers

Abstract Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.

Colloidal semiconductor nanocrystals: synthesis, optical nonlinearity, and related device applications

2021 ◽  
Author(s):  
Min Li ◽  
Cong Wang ◽  
Lude Wang ◽  
Han Zhang
Keyword(s):  
Nonlinear Optical ◽  
Rapid Development ◽  
Semiconductor Nanocrystals ◽  
Optical Nonlinearity ◽  
Photonic Devices ◽  
Nlo Properties ◽  
Novel Materials ◽  
Colloidal Semiconductor Nanocrystals ◽  
Device Applications ◽  
Colloidal Semiconductor

The rapid development of photonic devices requires the exploration of novel materials with superior nonlinear optical (NLO) properties. Colloidal semiconductor nanocrystals (NCs) exhibit size-tunable exciton resonances and excellent NLO properties....

Comparison of Pulsed Laser and Furnace Annealing of Nitrogen Implanted Silicon

1983 ◽  
Vol 23 ◽  
Author(s):  
T. P. Smith ◽  
P. J. Stiles ◽  
W. M. Augustyniak ◽  
W. L. Brown ◽  
D. C. Jacobson ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Polycrystalline Silicon ◽  
Laser Annealing ◽  
Semiconductor Device ◽  
Solid Phase ◽  
Pulsed Laser ◽  
Nitride Layer ◽  
High Dose ◽  
Infrared Transmission ◽  
Furnace Annealing

ABSTRACTFormation of buried insulating layers and redistribution of impurities during annealing are important processes in new semiconductor device technologies. We have studied pulsed ruby laser and furnace annealing of high dose (D>1017 N/cm2) 50 KeV nitrogen implanted silicon. Using He Back scattering and channeling, X-ray diffraction, transmission electron microscopy, and infrared transmission spectroscopy, we have compared liquid and solid phase regrowth, diffusion, impurity segregation and nitride formation. As has been previously reported, during furnace annealing at or above 1200C nitrogen redistributes and forms a polycrystalline silicon nitride (Si3N4 ) layer. [1–4] In contrast, pulsed laser annealing produces a buried amorphous silicon nitride layer filled with voids or bubbles below a layer of polycrystalline silicon.

Non-Destructive Measurements of III-V Semiconductor Device Structure by a Hard X-ray Microprobe

1991 ◽  
Vol 240 ◽  
Author(s):  
F. Uchida ◽  
J. Shigeta ◽  
Y. SUZUKI
Keyword(s):  
Semiconductor Device ◽  
Film Structure ◽  
Device Structure ◽  
X Ray ◽  
Model Sample ◽  
Device Structures ◽  
The Difference ◽  
X Ray Absorption ◽  
Non Destructive ◽  
Non Destructive Characterization

ABSTRACTA non-destructive characterization technique featuring a hard X-ray Microprobe is demonstrated for lll-V semiconductor device structures. A GaAs FET with a 2 μm gate length is measured as a model sample of a thin film structure. X-ray scanning microscopic images of the FET are obtained by diffracted X-ray and fluorescence X-ray detection. Diffracted X-ray detection measures the difference in gate material and source or drain material as a gray level difference on the image due to the X-ray absorption ratio. Ni Ka fluorescence detection, on the other hand, provides imaging of 500 Å thick Ni layers, which are contained only in the source and drain metals, through non-destructive observation.

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