Intelligent Wireless Ultrasonic Device for Damage Detection of Metallic Structures

In today’s world, it is necessary to monitor structures for possible damages. A failure to monitor the structures properly can cause structural catastrophe. Many researchers have worked on the low-power ultrasonic device to monitor the structures. In this research, we present an intelligent ultrasonic device (IUD) to monitor and detect the damages on the structures. The device uses microcontroller, actuator interface circuit, sensor interface circuit and radio frequency (RF) modem. The microcontroller has in-built high-speed analog-to-digital converter (ADC), digital-to-analog converter (DAC) and floating-point unit for signal processing. The controller generates the tone-burst signal and sends it to actuator interface circuit. The actuator interface circuit conditions the received signal from the microcontroller and drives the Piezoelectric Transducer (PZT) actuator. The actuator generates an ultrasonic wave in the structure. The wave is then sensed by PZT sensors. The sensor interface circuit selects the signal from desired PZT sensor and sends it to the microcontroller for further processing. The microcontroller digitizes the signal and computes the damage index and only if the damage is severe, it will send data wirelessly to the nearby PC. To test the device, iron specimen was prepared, PZT actuator and PZT sensor was mounted on it. The artificial crack was then induced on the specimen. The ultrasonic wave was then collected from the structure. By analyzing the ultrasonic wave, the device successfully detected the induced crack in the structure. The future work will be to use GSM modem so that the device can be monitored in the real time from the remote location.

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A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽

10.3390/s21072260 ◽

2021 ◽

Vol 21 (7) ◽

pp. 2260

Author(s):

Khuram Shehzad ◽

Deeksha Verma ◽

Danial Khan ◽

Qurat Ul Ain ◽

Muhammad Basim ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Intelligent Transportation System ◽

Cmos Process ◽

Process Technology ◽

Back Issue ◽

Digital To Analog Converter ◽

Analog To Digital ◽

Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL ◽

10.37394/23203.2022.17.1 ◽

2022 ◽

Vol 17 ◽

pp. 1-15

Author(s):

G. Vasudeva ◽

B. V. Uma

Keyword(s):

Low Power ◽

High Speed ◽

Performance Metrics ◽

Sampling Rate ◽

Geometrical Parameters ◽

Design Strategies ◽

Digital To Analog Converter ◽

Analog To Digital ◽

Transconductance Amplifier ◽

And Performance

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

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Low Area and High Bit Resolution Flash Analog to Digital Converter for Wide Band Applications: A Review

Micro and Nanosystems ◽

10.2174/1876402913666210820111312 ◽

2021 ◽

Vol 13 ◽

Author(s):

Banoth Krishna ◽

Sandeep Singh Gill ◽

Amod Kumar

Keyword(s):

High Speed ◽

Wide Band ◽

Low Noise ◽

Analog To Digital Converter ◽

Digital Converter ◽

Digital To Analog Converter ◽

Flash Adc ◽

Analog To Digital ◽

Power Efficient ◽

Low Area

: This work reviews the design challenges of CMOS flash type analog-to-digital converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter(DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.

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Integrated circuit design techniques for high-speed low-power analog-to-digital converters and on-chip calibration of sensor interface circuits

10.17760/d20254741 ◽

2017 ◽

Author(s):

Seyed Alireza Zahrai

Keyword(s):

Low Power ◽

Circuit Design ◽

Integrated Circuit ◽

High Speed ◽

Integrated Circuit Design ◽

Interface Circuits ◽

Sensor Interface ◽

Analog To Digital ◽

Sensor Interface Circuits ◽

On Chip

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A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

International Journal of Circuits, Systems and Signal Processing ◽

10.46300/9106.2021.15.62 ◽

2021 ◽

Vol 15 ◽

pp. 556-568

Author(s):

Chaya Shetty ◽

M. Nagabushanam ◽

Venkatesh Nuthan Prasad

Keyword(s):

High Speed ◽

Signal To Noise Ratio ◽

Sampling Rate ◽

Cmos Technology ◽

Sar Adc ◽

Cmos Process ◽

Digital To Analog Converter ◽

Additional Advantage ◽

Analog To Digital ◽

Split Capacitor

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

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The bright future of digital imaging in scanning electron microscopy

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100149672 ◽

1993 ◽

Vol 51 ◽

pp. 768-769

Author(s):

M. T. Postek ◽

A. E. Vladar

Keyword(s):

Electron Microscopy ◽

Scanning Electron Microscopy ◽

Digital Imaging ◽

High Speed ◽

High Performance ◽

Mass Storage ◽

Analog To Digital ◽

Central Processing ◽

Digital Imaging Technology ◽

Scanning Electron

One of the major advancements applied to scanning electron microscopy (SEM) during the past 10 years has been the development and application of digital imaging technology. Advancements in technology, notably the availability of less expensive, high-density memory chips and the development of high speed analog-to-digital converters, mass storage and high performance central processing units have fostered this revolution. Today, most modern SEM instruments have digital electronics as a standard feature. These instruments, generally have 8 bit or 256 gray levels with, at least, 512 × 512 pixel density operating at TV rate. In addition, current slow-scan commercial frame-grabber cards, directly applicable to the SEM, can have upwards of 12-14 bit lateral resolution permitting image acquisition at 4096 × 4096 resolution or greater. The two major categories of SEM systems to which digital technology have been applied are:In the analog SEM system the scan generator is normally operated in an analog manner and the image is displayed in an analog or "slow scan" mode.

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