Advanced Electrical Characterization of 90 nm Soft Bit Failure by Nano Probing Technique

2005 ◽  
Author(s):  
Christelle Giret ◽  
Damien Faure
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Electrical Measurements ◽  
Device Failure ◽  
Sram Cell ◽  
Visual Defects ◽  
Difficult Challenge ◽  
Type Of Failure

Abstract The Soft Bit failure (Single Bit Failure sensitive to voltage) of a 90nm SRAM cell presented a difficult challenge for the Failure Analysis (FA) group. Physical analysis of these Soft SRAM failures did not show any visual defects; therefore the FA required an accurate electrical characterization. The transistor characteristics of the failing SRAM transistors are needed in order to speculate on the possible failure mechanism. The Nano-Probing technique performed at Nice Device Failure Analysis of Laboratory (NDAL) allowed us to identify anomalies of I/V characteristics like Vt imbalance, low Gain, asymmetrical Vt, ID (Drive current) and Ron. Case studies of an asymmetry phenomenon reported here lead to a correlation between the failure mode and the electrical measurements. This paper demonstrates a suitable electrical methodology and characterization by Nano-Probing in order to successfully manage a FA approach on this type of failure.

Combination of SCM/SSRM Analysis and Nanoprobing Technique for Soft Single Bit Failure Analysis

2004 ◽  
Author(s):  
Larry Liu ◽  
Yuguo Wang ◽  
Hal Edwards ◽  
David Sekel ◽  
Dan Corum
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Site Isolation ◽  
Electrical Failure ◽  
The Past ◽  
Soft Failure ◽  
Sram Cell ◽  
Microscopy Analysis ◽  
Map Location

Abstract Traditionally, many semiconductor companies have used SRAM memory to develop their process technologies. The job of the failure analyst is often to physically deprocess the sample and hope to find the defect with only the bit map location to guide them. The success rate has been better in the past when the size of these SRAM cell were bigger. With the technology shrinking every 2 years, the chance of finding physical defects has become less and less. Besides the shrinking SRAM cell geometries, the electrical failure signature for many of the failures is marginal (soft failure), presenting difficult challenges for failure analysis (FA). Physical analysis of these soft SRAM failures at the sub-100nm technologies is often non-visual without detailed isolation and electrical characterization. Therefore, additional techniques are needed to improve the successful FA on newer technologies. In this discussion, we will present the uses of both SCM/SSRM (scanning capacitance microscopy / scanning spreading resistance microscopy) analysis and nanoprobing technique for fail site isolation.

Nanoprobing Applications with Capacitance-Voltage and Pulsed Current-Voltage Measurements for Device Failure Analysis

2015 ◽  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Pulsed Current ◽  
Electrical Measurements ◽  
Device Failure ◽  
Mos Devices ◽  
Atomic Force ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Rising Time

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

scholarly journals Individualization and Electrical Characterization of SiGe Nanowires

2012 ◽  
Vol 1408 ◽  
Author(s):  
M. Monasterio ◽  
A. Rodríguez ◽  
T. Rodríguez ◽  
C. Ballesteros
Keyword(s):  
Electrical Characterization ◽  
Ex Situ ◽  
Electrical Measurements ◽  
Measured Resistance ◽  
Single Nanowires ◽  
Very High

ABSTRACTSiGe nanowires of different Ge atomic fractions up to 15% were grown and ex-situ n-type doped by diffusion from a solid source in contact with the sample. The phenomenon of dielectrophoresis was used to locate single nanowires between pairs of electrodes in order to carry out electrical measurements. The measured resistance of the as-grown nanowires is very high, but it decreases more than three orders of magnitude upon doping, indicating that the doping procedure used has been effective.

Scanning Capacitance Microscopy for Failure Analysis of SOI-Based Advanced Microprocessors

2010 ◽  
Author(s):  
Lim Soon Huat ◽  
Lwin Hnin-Ei ◽  
Vinod Narang ◽  
J.M. Chin
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
Large Area ◽  
Scanning Capacitance Microscopy ◽  
Electrical Failure ◽  
Silicon Transistors ◽  
Soi Substrates ◽  
Electrical Data

Abstract Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.

Near-field Scanning Microwave Probe for Rapid Detection of Nonvisual and Parametric Defects in Cu/low-k Interconnect on Production Wafers

2006 ◽  
Author(s):  
Vladimir V. Talanov ◽  
Andrew R. Schwartz
Keyword(s):  
Failure Analysis ◽  
Rapid Detection ◽  
Near Field ◽  
Electrical Measurements ◽  
Visual Defects ◽  
Microwave Probe ◽  
Near Field Scanning ◽  
Low K

Abstract We demonstrate the use of a near-field scanned microwave probe (NSMP) for failure analysis (FA) of parametric defects in Cu/low-k interconnect that leave no physical remnant (sometimes referred to as “non-visual defects”). This technique is rapid, quantitative, non-contact, and provides direct electrical measurements.

Failure Analysis of Tungsten Stud Defect from the CMP Process

2000 ◽  
Author(s):  
K. Takagi ◽  
Y. Kohno ◽  
S. Nukii
Keyword(s):  
Electron Microscopy ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Open Circuit ◽  
Physical Analysis ◽  
Metal Line ◽  
Cross Sectional ◽  
Defect Isolation

Abstract This paper describes a failure analysis that effectively combined multiple analytic techniques to find the cause of I/O leakage in a flawed chip produced for an OEM (Original Equipment Manufacturer) product. Internal probing was initially used for defect isolation and a Tungsten (W) stud open circuit flaw was isolated by electrical characterization with internal probing. SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy, and FE-AES (Field Emission Auger Electron Spectroscopy) analysis with FIB (Focused Ion Beam) preparation were used for physical analysis. Cross-sectional SEM and TEM observations showed a gap with foreign material (FM) between the bottom of the metal line and the top of the W stud, possibly from the W CMP (chemical mechanical polish) process. FE-AES is effective for the analysis of light materials and their chemical composition, so a flat milling FIB process was used to prepare a cross-section for FE-AES analysis of the FM and the interfaces of the open defect. The spectra showed that the FM was traceable to the W CMP process. From these analytical results and problem reproduction experiments in the W CMP process on the manufacturing line, the failure mechanism was identified.

Electrical Characterization of a Double Barrier Direct Tunneling Diode Structure

1999 ◽  
Vol 567 ◽  
Author(s):  
E. M. Dons ◽  
C. S. Skowronski ◽  
K. R. Farmer
Keyword(s):  
Nonvolatile Memory ◽  
Electrical Characterization ◽  
Diode Structure ◽  
Electrical Measurements ◽  
Si Substrates ◽  
Direct Tunneling ◽  
Tunneling Diode ◽  
Nonvolatile Memory Devices ◽  
Interface Potential

ABSTRACTWe report the electrical characterization of a direct tunneling diode structure that incorporates a multilayer dielectric. The dielectric consists of a stack of two thermally grown, ultrathin SiO2 layers, each ∼3.5 rin thick, separated by a deposited, continuous, undoped, ultrathin nanocrystalline Si layer ∼5.0 nm thick. Electrical measurements of this structure are reported for both n-type and p-type Si substrates. We find that the room temperature transport through this structure is accounted for by describing the intermediate Si layer as a quantum well with a continuum of states, and by otherwise assuming bulk properties for the ultrathin layers, such as the existence of a bandgap in the Si well and the usual Si-SiO2 interface potential barrier height at all interfaces. This structure is expected to be useful as the active dielectric in nonvolatile memory devices.

Electrical Characterization of MOS Structures with Silicon Nanocrystals Suitable for X-Ray Detection

2013 ◽  
Vol 543 ◽  
pp. 150-153
Author(s):  
David Mateos ◽  
Nicola Nedev ◽  
Diana Nesheva ◽  
Mario Curiel ◽  
Emil Manolov ◽  
...  
Keyword(s):  
Silicon Nanocrystals ◽  
Gate Dielectric ◽  
Defect Density ◽  
Electrical Characterization ◽  
Oxide Semiconductor ◽  
Electrical Measurements ◽  
Transmission Electron ◽  
Interface Defect ◽  
Mos Structures

Metal-Oxide-Semiconductor structures with silicon nanocrystals in the oxide layer are prepared and characterized by Transmission Electron Microscopy and electrical measurements. High temperature annealing of SiO1.15 films at 1000 °C for 30 or 60 min leads to formation of silicon nanocrystals with diameters of 2-3 or 4-6 nm. The processes used to obtain the multilayer gate dielectric and to grow nanocrystals do not deteriorate the properties of the cSi wafer/thermal SiO2 interface. For the interface defect density and the fixed oxide charge values 1010 cm-2 eV-1 and ~ 1010 cm-2 were obtained.

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