Combination of SCM/SSRM Analysis and Nanoprobing Technique for Soft Single Bit Failure Analysis

2004 ◽  
Author(s):  
Larry Liu ◽  
Yuguo Wang ◽  
Hal Edwards ◽  
David Sekel ◽  
Dan Corum
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Site Isolation ◽  
Electrical Failure ◽  
The Past ◽  
Soft Failure ◽  
Sram Cell ◽  
Microscopy Analysis ◽  
Map Location

Abstract Traditionally, many semiconductor companies have used SRAM memory to develop their process technologies. The job of the failure analyst is often to physically deprocess the sample and hope to find the defect with only the bit map location to guide them. The success rate has been better in the past when the size of these SRAM cell were bigger. With the technology shrinking every 2 years, the chance of finding physical defects has become less and less. Besides the shrinking SRAM cell geometries, the electrical failure signature for many of the failures is marginal (soft failure), presenting difficult challenges for failure analysis (FA). Physical analysis of these soft SRAM failures at the sub-100nm technologies is often non-visual without detailed isolation and electrical characterization. Therefore, additional techniques are needed to improve the successful FA on newer technologies. In this discussion, we will present the uses of both SCM/SSRM (scanning capacitance microscopy / scanning spreading resistance microscopy) analysis and nanoprobing technique for fail site isolation.

Advanced Electrical Characterization of 90 nm Soft Bit Failure by Nano Probing Technique

2005 ◽  
Author(s):  
Christelle Giret ◽  
Damien Faure
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Electrical Measurements ◽  
Device Failure ◽  
Sram Cell ◽  
Visual Defects ◽  
Difficult Challenge ◽  
Type Of Failure

Abstract The Soft Bit failure (Single Bit Failure sensitive to voltage) of a 90nm SRAM cell presented a difficult challenge for the Failure Analysis (FA) group. Physical analysis of these Soft SRAM failures did not show any visual defects; therefore the FA required an accurate electrical characterization. The transistor characteristics of the failing SRAM transistors are needed in order to speculate on the possible failure mechanism. The Nano-Probing technique performed at Nice Device Failure Analysis of Laboratory (NDAL) allowed us to identify anomalies of I/V characteristics like Vt imbalance, low Gain, asymmetrical Vt, ID (Drive current) and Ron. Case studies of an asymmetry phenomenon reported here lead to a correlation between the failure mode and the electrical measurements. This paper demonstrates a suitable electrical methodology and characterization by Nano-Probing in order to successfully manage a FA approach on this type of failure.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

2002 ◽  
Author(s):  
Hui Pan ◽  
Thomas Gibson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Charge Pump ◽  
Front Side ◽  
Pump Failure ◽  
Electrical Failure ◽  
Optical Proximity Correction ◽  
A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

The SRAM Soft Failure Analysis with SNM & TR Characterization by Nanoprobing in Sub 45nm

2009 ◽  
Author(s):  
Jakyung Hong ◽  
S.J. Cho ◽  
Y.W. Han ◽  
H.S. Choi ◽  
T.E. Kim ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Metal Layer ◽  
Noise Margin ◽  
Soft Failure ◽  
Sram Cell ◽  
Cell Stability ◽  
The Stability ◽  
Static Noise

Abstract This paper presents the process of measuring static noise margin (SNM), write noise margin (WNM) with 6 pin nanoprober, and characterization and analysis of SRAM cell stability through case studies of 45nm devices SRAM soft failures. It highlights that the local mismatch in the bit cell caused by slight variations in the transistor characteristics, such as Vth shift and Idsat, off variation, also can easily induce a soft failure. The analysis of the SNM TR characteristic is successfully demonstrated through the case study of 45nm SRAM devices. The chapter explains SNM measurement in the metal layer and transistor measurements in the CA layer. Measuring the SNM TR's characteristics is an important methodology in understanding the stability of each bit cell and failure mechanism depending on voltage, defects, and other factors. The next generation of nanoprobing analysis can be expanded.

Scanning Capacitance Microscopy for Failure Analysis of SOI-Based Advanced Microprocessors

2010 ◽  
Author(s):  
Lim Soon Huat ◽  
Lwin Hnin-Ei ◽  
Vinod Narang ◽  
J.M. Chin
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
Large Area ◽  
Scanning Capacitance Microscopy ◽  
Electrical Failure ◽  
Silicon Transistors ◽  
Soi Substrates ◽  
Electrical Data

Abstract Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.

Failure Analysis of Tungsten Stud Defect from the CMP Process

2000 ◽  
Author(s):  
K. Takagi ◽  
Y. Kohno ◽  
S. Nukii
Keyword(s):  
Electron Microscopy ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Open Circuit ◽  
Physical Analysis ◽  
Metal Line ◽  
Cross Sectional ◽  
Defect Isolation

Abstract This paper describes a failure analysis that effectively combined multiple analytic techniques to find the cause of I/O leakage in a flawed chip produced for an OEM (Original Equipment Manufacturer) product. Internal probing was initially used for defect isolation and a Tungsten (W) stud open circuit flaw was isolated by electrical characterization with internal probing. SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy, and FE-AES (Field Emission Auger Electron Spectroscopy) analysis with FIB (Focused Ion Beam) preparation were used for physical analysis. Cross-sectional SEM and TEM observations showed a gap with foreign material (FM) between the bottom of the metal line and the top of the W stud, possibly from the W CMP (chemical mechanical polish) process. FE-AES is effective for the analysis of light materials and their chemical composition, so a flat milling FIB process was used to prepare a cross-section for FE-AES analysis of the FM and the interfaces of the open defect. The spectra showed that the FM was traceable to the W CMP process. From these analytical results and problem reproduction experiments in the W CMP process on the manufacturing line, the failure mechanism was identified.

Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System

2016 ◽  
Author(s):  
Li-Qing Chen ◽  
Ming-Sheng Sun ◽  
Jui-Hao Chao ◽  
Soon Fatt Ng ◽  
Kapilevich Izak ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Photon Emission ◽  
Wafer Level ◽  
Success Story ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Soft Failure ◽  
Scan Chain ◽  
Hard Failure

Abstract This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

Failure Analysis of Soft Single Column Failure in Advanced Nano SRAM Device with Internal Probing Techniques

2005 ◽  
Author(s):  
Hung-Sung Lin ◽  
Wen-Tung Chang ◽  
Chia-Hsing Chao ◽  
Jesse Wang ◽  
Chang-Tan Lin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Modes ◽  
Electrical Characterization ◽  
Conductive Atomic Force Microscopy ◽  
Resistance Change ◽  
Electrical Failure ◽  
Force Microscopy ◽  
Root Cause ◽  
Atomic Force ◽  
Single Column

Abstract Single column failure [1], one of the complex failure modes in SRAM is possibly induced by multiform defect types at diverse locations. Especially, soft single column failure is of great complexity. As physical failure analysis (PFA) is expensive and time-consuming, thorough electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad Telluride, HgCdTe) for analysis. However, the electrical failure signature for soft single column failure is usually marginal, so additional techniques are needed to obtain accurate isolation and electrical characterization instead of blindly looking around. Thus in this discussion, we will also present the use of internal probing techniques like C-AFM [2] (Conductive Atomic Force Microscopy) and a nanoprobing technique [3] for characterizing electrical properties and understanding the root cause.

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

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