Analysis of a Microcircuit Failure using SQUID and MR Current Imaging

2005 ◽  
Author(s):  
Frederick S. Felt
Keyword(s):  
Integrated Circuits ◽  
Thermal Emission ◽  
High Current Density ◽  
Fault Isolation ◽  
Magnetic Sensors ◽  
Nand Gate ◽  
Magnetic Current ◽  
Package Design ◽  
Low Resistance ◽  
Current Path

Abstract SQUID and MR magnetic sensors have separately been used for fault isolation of shorts and resistive opens in integrated circuits and packages. These two technologies were once considered to be mutually exclusive, although recent studies [1] rather pointed to their complementary character. This paper shows, for the first time, the use of these two sensors together to isolate a low resistance short in a Quad-NAND gate microcircuit. Electrical test confirmed low resistance shorts between three of the device pins. However, internal optical inspection found no evidence of failure. The low resistance of the shorts was deemed insufficient for liquid crystal analysis. Magnetic current imaging with a SQUID sensor confirmed current flow through the package lead frame and isolated the defect to the microcircuit. Due to package design and the resulting distance of the scan plane, the SQUID was unable to resolve the current path on the microcircuit. In parallel with the SQUID, a magnetoresistive (MR) probe was employed to fit inside the device cavity, make direct contact with the microcircuit, and map high-resolution current images. Two sites with high-current density were accurately identified by MCI in input transistors. Subsequent deprocessing revealed that the defects were located under a broad sheet of aluminum metallization which blocked optical detection, and rendered detection by thermal emission difficult.

Construction of a 3-D Current Path Using Magnetic Current Imaging

2007 ◽  
Author(s):  
Frederick Felt ◽  
Lee Knauss ◽  
Anders Gilbertson ◽  
Antonio Orozco
Keyword(s):  
Three Dimensional ◽  
Form Factors ◽  
Fault Isolation ◽  
Magnetic Sensors ◽  
Physical Analysis ◽  
Magnetic Current ◽  
Nasa Goddard Space ◽  
Current Path ◽  
Multiple Devices ◽  
Board Level

Abstract The need to miniaturize in the electronics industry is driving smaller form factors, and resulting in complex packaging innovations such as structures with multiple devices stacked inside a three dimensional package. These structures present a challenge for non-destructive fault isolation. Two such modules recently exhibited failures on the NASA Goddard Space Flight Center Solar Dynamic Observatory (SDO) during board-level testing. Each module consisted of eight vertically-stacked mini-boards, each mini-board with a single EEPROM microcircuit and capacitor, and connected by external gold metallization to module pins. Both failed modules exhibited low-resistance shorts between multiple pins. The orthogonal structure of the module prompted the use of magnetic current imaging (MCI) in three planes in order to construct an internal three-dimensional current path for each of the failed modules. Magnetic current imaging is able to “look through” non-magnetic, or de-gaussed packaging materials, allowing global imaging without physical deprocessing of the stacked EEPROM modules, in order to construct the internal current path and localize defects. To our knowledge, this is the first time that this has been done. Following global isolation of the defects, two types of magnetic sensors were used in parallel with limited deprocessing in order to more precisely characterize suspect failure locations before actually physically exposing the defects. This paper will show the process for using magnetic current imaging with both SQUID and magnetoresistive (GMR) sensors to isolate defects in two stacked EEPROM packages along with the final physical analysis of the defects. The failure analysis found that these devices were damaged by external heat, possibly during oven pre-conditioning or hot air soldering onto the board. The manufacturer, 3-D Plus, was not implicated in the failure.

Magnetic Current Imaging of a TSV short in a 3D IC

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001408-001428
Author(s):  
Jan Gaudestad ◽  
Antonio Orozco
Keyword(s):  
Quantum Interference ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Current Path ◽  
Fine Pitch ◽  
Dual Beam ◽  
Gmr Sensor ◽  
Test Chips ◽  
Chip Chip

In this paper we show Magnetic Field Imaging (MFI) is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a Dual Beam-Plasma FIB (DB-PFIB) system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. Magnetic Current Imaging (MCI) is a sub technique of MFI which has been used by the semiconductor industry for more than a decade to find electrical shorts and leakage paths and which has the capability to “look through” all materials typically used in the semiconductor industry, allowing global imaging without the need for physical de-processing [1, 2, 3]. MCI utilizes two types of sensors: a Superconducting Quantum Interference Device (SQUID) sensor for low current and large working distances and a Giant Magneto Resistance (GMR) sensor for sub micron resolution current imaging at wafer/die level [3]. The sample investigated in this work is a triple-layer stack, in which 2 layers of 50 μm thick test chip (Chip 1 and Chip 2 in Figure 1) were assembled on a 200 μm thick bottom chip (Chip 0 in Figure 1). The test chips were manufactured by imec's standard 65 nm CMOS Back End of Line (BEOL) process, 5×50 μm via-middle TSV technology [4], and fine pitch micro bumping process [6]. Further details of the test vehicle and assembly process can be found elsewhere [5]. The sample had a short between daisy chain a1 and a2, which were supposed to be electrically separated. The probe tests that was used for this experiment is shown in Table 1. The signal was injected into the respective daisy chains by probing V+ to V− on the bottom chip. To send a signal between daisy chain a1 and a2 one could probe V− to V− and V+ to V+. The MCI scans were done using the GMR sensor only. The sample was attached to a vacuum chuck and raster scanned. From Fig. 2 one can see that the current enters the top layer (Chip 2) at TSV 18 and goes back down again to Chip 1 at TSV 28. Since the sample clearly has multiple shorts, the short located at TSV pair 23 was chosen for PFA using the PFIB. A short is found between the 2 BEOL layers of Chip 1, causing the current to leak into Chip 2 (Fig. 3).

Thermal Failure Analysis of Functional Failures by IR Lock-in Thermal Emission

2019 ◽  
Author(s):  
Paul Hubert P. Llamera ◽  
Camille Joyce G. Garcia-Awitan
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Near Infrared ◽  
Thermal Emission ◽  
Fault Localization ◽  
Fault Isolation ◽  
Distinct Advantage ◽  
Infra Red ◽  
Emission Microscopy ◽  
Lock In

Abstract Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.

Short Localization in 2.5D Microchip with Interposer Using Magnetic Current Imaging

2014 ◽  
Author(s):  
J. Gaudestad ◽  
D. Nuez ◽  
P. Tan
Keyword(s):  
Magnetic Fields ◽  
Integrated Circuits ◽  
Semiconductor Manufacturing ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Solder Bumps ◽  
New Challenges ◽  
Materials Used ◽  
Silicon Vias ◽  
Metal Layers

Abstract Interposers used in 2.5D technologies introduce new challenges for Electric Fault Isolation (EFI) due to the multiple layers of silicon, metal layers, Through Silicon Vias (TSV), solder bumps and/or copper pillars making it hard for standard EFI techniques, such as thermal and optical techniques, to localize failures due to the opaqueness of these materials [1, 2, 3]. In this paper we show that shorts in 2.5D Integrated Circuits (IC) technologies can be localized accurately in x, y and z-direction using Magnetic Current Imaging (MCI) while injecting a low power current and showing that the materials used in 2.5D semiconductor manufacturing are fully transparent to magnetic fields.

Scanning Magnetoresistive Microscopy for Die-Level Sub-Micron Current Density Mapping

2003 ◽  
Author(s):  
B. D. Schrag ◽  
X. Y. Liu ◽  
M. J. Carter ◽  
Gang Xiao
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Spatial Resolution ◽  
Current Density ◽  
Imaging System ◽  
Fault Isolation ◽  
Magnetic Sensors ◽  
Density Mapping ◽  
Current Densities ◽  
A New Technique

Abstract In this paper, we will present a new technique for fault isolation and failure analysis in integrated circuits based on a scanning magnetoresistive imaging system. By detecting the stray magnetic fields at the surface of a chip using magnetic sensors with sub-micron spatial resolution, we are able to obtain a full map of in-plane current densities, resolving features smaller than 100 nanometers. We will briefly discuss the capabilities and limitations of the technique and will present results on a variety of frontside and backside samples.

Advanced Non-Destructive Fault Isolation Techniques for PCB Substrates Using Magnetic Current Imaging and Terahertz Time Domain Reflectometry

2018 ◽  
Author(s):  
Daechul Choi ◽  
Yoonseong Kim ◽  
Jongyun Kim ◽  
Han Kim
Keyword(s):  
Time Domain ◽  
Quantum Interference ◽  
Flip Chip ◽  
Imaging System ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Isolation Techniques ◽  
Super Conducting ◽  
Non Destructive

Abstract In this paper, we demonstrate cases for actual short and open failures in FCB (Flip Chip Bonding) substrates by using novel non-destructive techniques, known as SSM (Scanning Super-conducting Quantum Interference Device Microscopy) and Terahertz TDR (Time Domain Reflectometry) which is able to pinpoint failure locations. In addition, the defect location and accuracy is verified by a NIR (Near Infra-red) imaging system which is also one of the commonly used non-destructive failure analysis tools, and good agreement was made.

Root Cause Analysis Techniques Using Picosecond Time Resolved LADA

2014 ◽  
Author(s):  
Dan Bodoh ◽  
Kent Erington ◽  
Kris Dickson ◽  
George Lange ◽  
Carey Wu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Picosecond Laser ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
Time Resolved ◽  
Cause Analysis ◽  
Root Cause ◽  
Design And Manufacturing ◽  
Multiple Interactions ◽  
Established Technique

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

Magnetic Current Imaging Power Short Localization

2015 ◽  
Author(s):  
J. Gaudestad ◽  
F. Rusli ◽  
A. Orozco ◽  
M.C. Pun
Keyword(s):  
Thermal Imaging ◽  
Flip Chip ◽  
Optical Microscope ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Multiple Fault ◽  
Defect Location ◽  
Isolation Techniques ◽  
Chip Sample

Abstract A Flip Chip sample failed short between power and ground. The reference unit had 418Ω and the failed unit with the short had 16.4Ω. Multiple fault isolation techniques were used in an attempt to find the failure with thermal imaging and Magnetic Current Imaging being the only techniques capable of localizing the defect. To physically verify the defect location, the die was detached from the substrate and a die cracked was seen using a visible optical microscope.

Fault Isolation of Open Defects Using Space Domain Reflectometry

2012 ◽  
Author(s):  
Mayue Xie ◽  
Zhiguo Qian ◽  
Mario Pacheco ◽  
Zhiyong Wang ◽  
Rajen Dias ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Fault Isolation ◽  
Nondestructive Technique ◽  
Space Domain ◽  
New Approach ◽  
Defect Localization ◽  
Open Faults ◽  
Open Defects ◽  
Application Optimization ◽  
Rf Magnetic Field

Abstract Recently, a new approach for isolation of open faults in integrated circuits (ICs) was developed. It is based on mapping the radio-frequency (RF) magnetic field produced by the defective part fed with RF probing current, giving the name to Space Domain Reflectometry (SDR). SDR is a non-contact and nondestructive technique to localize open defects in package substrates, interconnections and semiconductor devices. It provides 2D failure isolation capability with defect localization resolution down to 50 microns. It is also capable of scanning long traces in Si. This paper describes the principles of the SDR and its application for the localization of open and high resistance defects. It then discusses some analysis methods for application optimization, and gives examples of test samples as well as case studies from actual failures.

Magnetic Current Imaging Techniques: Comparative Case Studies

2004 ◽  
Author(s):  
Olivier Crépel ◽  
Philippe Descamps ◽  
Patrick Poirier ◽  
Romain Desplats ◽  
Philippe Perdu ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Integrated Circuits ◽  
Case Studies ◽  
Flip Chip ◽  
Imaging Techniques ◽  
Optimal Domain ◽  
Magnetic Current ◽  
Comparative Case Studies ◽  
Current Flows

Abstract Magnetic field based techniques have shown great capabilities for investigation of current flows in integrated circuits (ICs). After reviewing the performances of SQUID, GMR (hard disk head technologies) and MTJ existing sensors, we will present results obtained on various case studies. This comparison will show the benefit of each approach according to each case study (packaged devices, flip-chip circuits, …). Finally we will discuss on the obtained results to classify current techniques, optimal domain of applications and advantages.

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