Construction of a 3-D Current Path Using Magnetic Current Imaging

2007 ◽  
Author(s):  
Frederick Felt ◽  
Lee Knauss ◽  
Anders Gilbertson ◽  
Antonio Orozco
Keyword(s):  
Three Dimensional ◽  
Form Factors ◽  
Fault Isolation ◽  
Magnetic Sensors ◽  
Physical Analysis ◽  
Magnetic Current ◽  
Nasa Goddard Space ◽  
Current Path ◽  
Multiple Devices ◽  
Board Level

Abstract The need to miniaturize in the electronics industry is driving smaller form factors, and resulting in complex packaging innovations such as structures with multiple devices stacked inside a three dimensional package. These structures present a challenge for non-destructive fault isolation. Two such modules recently exhibited failures on the NASA Goddard Space Flight Center Solar Dynamic Observatory (SDO) during board-level testing. Each module consisted of eight vertically-stacked mini-boards, each mini-board with a single EEPROM microcircuit and capacitor, and connected by external gold metallization to module pins. Both failed modules exhibited low-resistance shorts between multiple pins. The orthogonal structure of the module prompted the use of magnetic current imaging (MCI) in three planes in order to construct an internal three-dimensional current path for each of the failed modules. Magnetic current imaging is able to “look through” non-magnetic, or de-gaussed packaging materials, allowing global imaging without physical deprocessing of the stacked EEPROM modules, in order to construct the internal current path and localize defects. To our knowledge, this is the first time that this has been done. Following global isolation of the defects, two types of magnetic sensors were used in parallel with limited deprocessing in order to more precisely characterize suspect failure locations before actually physically exposing the defects. This paper will show the process for using magnetic current imaging with both SQUID and magnetoresistive (GMR) sensors to isolate defects in two stacked EEPROM packages along with the final physical analysis of the defects. The failure analysis found that these devices were damaged by external heat, possibly during oven pre-conditioning or hot air soldering onto the board. The manufacturer, 3-D Plus, was not implicated in the failure.

Analysis of a Microcircuit Failure using SQUID and MR Current Imaging

2005 ◽  
Author(s):  
Frederick S. Felt
Keyword(s):  
Integrated Circuits ◽  
Thermal Emission ◽  
High Current Density ◽  
Fault Isolation ◽  
Magnetic Sensors ◽  
Nand Gate ◽  
Magnetic Current ◽  
Package Design ◽  
Low Resistance ◽  
Current Path

Abstract SQUID and MR magnetic sensors have separately been used for fault isolation of shorts and resistive opens in integrated circuits and packages. These two technologies were once considered to be mutually exclusive, although recent studies [1] rather pointed to their complementary character. This paper shows, for the first time, the use of these two sensors together to isolate a low resistance short in a Quad-NAND gate microcircuit. Electrical test confirmed low resistance shorts between three of the device pins. However, internal optical inspection found no evidence of failure. The low resistance of the shorts was deemed insufficient for liquid crystal analysis. Magnetic current imaging with a SQUID sensor confirmed current flow through the package lead frame and isolated the defect to the microcircuit. Due to package design and the resulting distance of the scan plane, the SQUID was unable to resolve the current path on the microcircuit. In parallel with the SQUID, a magnetoresistive (MR) probe was employed to fit inside the device cavity, make direct contact with the microcircuit, and map high-resolution current images. Two sites with high-current density were accurately identified by MCI in input transistors. Subsequent deprocessing revealed that the defects were located under a broad sheet of aluminum metallization which blocked optical detection, and rendered detection by thermal emission difficult.

Electrothermal coupling analysis and experimental verification for wirebond devices

2018 ◽  
Vol 42 (3) ◽  
pp. 268-279
Author(s):  
Chin-Li Kao ◽  
Tei-Chen Chen
Keyword(s):  
Thermal Performance ◽  
Failure Modes ◽  
Three Dimensional ◽  
Decomposition Temperature ◽  
Physical Analysis ◽  
Coupling Analysis ◽  
Heat Spreader ◽  
Molding Compound ◽  
Modeling Experiment ◽  
Board Level

The thermal performance of a powered wirebond device with package level and board level test specimens was investigated by both analytical and experiment methods. The effects of thickness and thermal conductivity of the molding compound and heat spreader attached to the top surface of the molding compound on the performance of the Au wire and silicon die were modeled and evaluated by three-dimensional electrothermal coupling analysis. An advanced quad flat no-lead (QFN) sample was selected to experimentally measure the maximum allowable current in Au wire for packages either with or without molding compound. Two failure modes, namely the fusing of the wire and the decomposition temperature of the molding compound, were established in analysis. A board level test specimen with a thermal test die was also employed to measure the real time package thermal performance. The major achievement of this work is in the complete combination of modeling, experiment, and optimization for thermal performance evaluation purpose of a powered wirebond device. Results of this physical analysis can provide a reliable and useful guide to estimate the maximum allowable currents in Au wires for a wirebond device under practical application conditions.

Magnetic Current Imaging of a TSV short in a 3D IC

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001408-001428
Author(s):  
Jan Gaudestad ◽  
Antonio Orozco
Keyword(s):  
Quantum Interference ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Current Path ◽  
Fine Pitch ◽  
Dual Beam ◽  
Gmr Sensor ◽  
Test Chips ◽  
Chip Chip

In this paper we show Magnetic Field Imaging (MFI) is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a Dual Beam-Plasma FIB (DB-PFIB) system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. Magnetic Current Imaging (MCI) is a sub technique of MFI which has been used by the semiconductor industry for more than a decade to find electrical shorts and leakage paths and which has the capability to “look through” all materials typically used in the semiconductor industry, allowing global imaging without the need for physical de-processing [1, 2, 3]. MCI utilizes two types of sensors: a Superconducting Quantum Interference Device (SQUID) sensor for low current and large working distances and a Giant Magneto Resistance (GMR) sensor for sub micron resolution current imaging at wafer/die level [3]. The sample investigated in this work is a triple-layer stack, in which 2 layers of 50 μm thick test chip (Chip 1 and Chip 2 in Figure 1) were assembled on a 200 μm thick bottom chip (Chip 0 in Figure 1). The test chips were manufactured by imec's standard 65 nm CMOS Back End of Line (BEOL) process, 5×50 μm via-middle TSV technology [4], and fine pitch micro bumping process [6]. Further details of the test vehicle and assembly process can be found elsewhere [5]. The sample had a short between daisy chain a1 and a2, which were supposed to be electrically separated. The probe tests that was used for this experiment is shown in Table 1. The signal was injected into the respective daisy chains by probing V+ to V− on the bottom chip. To send a signal between daisy chain a1 and a2 one could probe V− to V− and V+ to V+. The MCI scans were done using the GMR sensor only. The sample was attached to a vacuum chuck and raster scanned. From Fig. 2 one can see that the current enters the top layer (Chip 2) at TSV 18 and goes back down again to Chip 1 at TSV 28. Since the sample clearly has multiple shorts, the short located at TSV pair 23 was chosen for PFA using the PFIB. A short is found between the 2 BEOL layers of Chip 1, causing the current to leak into Chip 2 (Fig. 3).

Advanced Non-Destructive Fault Isolation Techniques for PCB Substrates Using Magnetic Current Imaging and Terahertz Time Domain Reflectometry

2018 ◽  
Author(s):  
Daechul Choi ◽  
Yoonseong Kim ◽  
Jongyun Kim ◽  
Han Kim
Keyword(s):  
Time Domain ◽  
Quantum Interference ◽  
Flip Chip ◽  
Imaging System ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Isolation Techniques ◽  
Super Conducting ◽  
Non Destructive

Abstract In this paper, we demonstrate cases for actual short and open failures in FCB (Flip Chip Bonding) substrates by using novel non-destructive techniques, known as SSM (Scanning Super-conducting Quantum Interference Device Microscopy) and Terahertz TDR (Time Domain Reflectometry) which is able to pinpoint failure locations. In addition, the defect location and accuracy is verified by a NIR (Near Infra-red) imaging system which is also one of the commonly used non-destructive failure analysis tools, and good agreement was made.

Magnetic Current Imaging Power Short Localization

2015 ◽  
Author(s):  
J. Gaudestad ◽  
F. Rusli ◽  
A. Orozco ◽  
M.C. Pun
Keyword(s):  
Thermal Imaging ◽  
Flip Chip ◽  
Optical Microscope ◽  
Fault Isolation ◽  
Magnetic Current ◽  
Multiple Fault ◽  
Defect Location ◽  
Isolation Techniques ◽  
Chip Sample

Abstract A Flip Chip sample failed short between power and ground. The reference unit had 418Ω and the failed unit with the short had 16.4Ω. Multiple fault isolation techniques were used in an attempt to find the failure with thermal imaging and Magnetic Current Imaging being the only techniques capable of localizing the defect. To physically verify the defect location, the die was detached from the substrate and a die cracked was seen using a visible optical microscope.

Effect of TSV Joule Heating on Device Performance

2013 ◽  
Author(s):  
Fahad Mirza ◽  
Gaurang Naware ◽  
Thiagarajan Raman ◽  
Ankur Jain ◽  
Dereje Agonafer
Keyword(s):  
Joule Heating ◽  
Heat Dissipation ◽  
Form Factors ◽  
Signal Propagation ◽  
Junction Temperature ◽  
Electrical Performance ◽  
Device Performance ◽  
Base Line ◽  
Heat Current ◽  
Current Path

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

Single-Phase Microchannel Cooling for Stacked Single Core Chip and DRAM

2011 ◽  
Author(s):  
Anjali Chauhan ◽  
Bahgat Sammakia ◽  
Kanad Ghose ◽  
Gamal Refai-Ahmed ◽  
Dereje Agonafer
Keyword(s):  
Thermal Resistance ◽  
Thermal Management ◽  
Heat Sink ◽  
Single Phase ◽  
Cooling System ◽  
Three Dimensional ◽  
Form Factors ◽  
Memory Access ◽  
Thermal Interface Material ◽  
Level Energy

The stacking of processing and memory components in a three-dimensional (3D) configuration enables the implementation of processing systems with small form factors. Such stacking shortens the interconnection length between processing and memory components to dramatically lower the memory access latencies, and contributes to significant improvements in the memory access bandwidth. Both of these factors elevate overall system performance to levels that are not realizable with prevailing and other proposed solutions. The shorter interconnection lengths in stacked architectures also enable the use of smaller drivers for the interconnections, which in turn reduces interconnection-level energy dissipations. On the down side, stacking of processing and memory components introduces a significant thermal management challenge that is rooted in the high thermal resistance of stacked designs. This paper examines and evaluates three distinct solutions that address thermal management challenges in a system that stacks DRAM components onto a processing core. We primarily focus on three different configurations of a microchannel-based single-phase liquid cooling system with a traditional air-cooled heat sink. Our evaluations, which are intended to study the limits of each solution, assume a uniform power dissipation model for the processor and accounts for the thermal resistance offered by the thermal interface material (TIM), the interconnect layer, and through-silicon vias (TSVs). The liquid-cooled microchannel heat sink shows more promising results when integrated into the package than when added to the microprocessor package from outside.

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