Cross Sectional Passive Voltage Contrast Approach for Gate Oxide Breakdown Defect Isolation and Visualization for TEM Analysis

2020 ◽  
Author(s):  
S.L. Ting ◽  
P.K. Tan ◽  
Y.L. Pan ◽  
H.H.W. Thoungh ◽  
S.Y. Thum ◽  
...  
Keyword(s):  
Complex Structure ◽  
Breakdown Point ◽  
Gate Oxide ◽  
Tem Analysis ◽  
Cross Sectional ◽  
Oxide Breakdown ◽  
Root Cause ◽  
Polysilicon Gate ◽  
Defect Isolation ◽  
Voltage Contrast

Abstract Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

2013 ◽  
Vol 740-742 ◽  
pp. 745-748 ◽  
Author(s):  
J. Sameshima ◽  
Osamu Ishiyama ◽  
Atsushi Shimozato ◽  
K. Tamura ◽  
H. Oshima ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Mos Capacitors ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Breakdown Region

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

Structure Of The Defects Responsible For B-Mode Breakdown Of Gate Oxide Grown On The Surface Of Silicon Wafers

1996 ◽  
Vol 442 ◽  
Author(s):  
T. Mera ◽  
J. Jablonski ◽  
M. Danbata ◽  
K. Nagai ◽  
M. Watanabe
Keyword(s):  
Gate Oxide ◽  
Wafer Surface ◽  
Cross Sectional ◽  
Oxide Breakdown ◽  
Breakdown Mechanism ◽  
Transmission Electron ◽  
Thermal Oxide ◽  
Before And After ◽  
Thick Oxide Layer ◽  
Unambiguous Detection

AbstractCrystal-originated pits are known as the defects responsible for B-mode Time Zero Dielectric Break-down (TZDB) of the gate oxide grown on the surface of Si wafers. In order to clarify the breakdown mechanism, we have analyzed the structure of those defects formed at the surface of bare and oxidized wafers. In the latter case the analysis has been done both before and after gate oxide breakdown. Electric breakdown has been accomplished by Cu decoration method, recognized as an effective tool for unambiguous detection and positioning of the defects causing B-mode TZDB. As revealed by cross-sectional transmission electron microscopy (XTEM), crystal-originated pits at the bare wafer surface are polyhedral pits having about 5-nm-thick oxide layer on the inner walls. During gate oxidation the thermal oxide is growing faster on the pit walls than on the wafer surface, except for the pit comers where the oxide thinning has been observed. Resulting concave comers of the oxidized pits are suggested to be the weak spots where B-mode TZDB occurs.

Effective Defect Localization on Nanoscale Short Failures

2013 ◽  
Author(s):  
Jiang Huang ◽  
Ryan Sweeney ◽  
Laurent Dumas ◽  
Mark Johnston ◽  
Pei-Yi Chen ◽  
...  
Keyword(s):  
High Resolution ◽  
Leading Edge ◽  
High Sensitivity ◽  
Silicon On Insulator ◽  
Nanometer Scale ◽  
Tem Analysis ◽  
Root Cause ◽  
Transmission Electron ◽  
High Resolution Tem ◽  
Voltage Contrast

Abstract This paper presents two case studies, based on 32nm Silicon-On-Insulator (SOI) and 28nm bulk Si technology, on finding the root cause of nanometer scale short failures using Passive Voltage Contrast (PVC), Active Voltage Contrast (AVC) and Transmission Electron Microscopy (TEM). PVC/AVC is used as precision localization technique that is critical for a successful FA-TEM analysis. Combining planar TEM sample preparation and high sensitivity Energy Dispersive Spectroscopy (EDS) mapping, a small residual filament, which is not visible even at high resolution TEM, is found to short two metal lines. The effective usage of voltage contrast and TEM provides the need of high throughput, high precision, and high resolution in the advanced FA lab that serves leading-edge semiconductor manufacturing.

An Effective and Practical Analysis Technique for Open Defect Isolation at IDD Leakage Failure by Observing Transient Photo Emission

1998 ◽  
Author(s):  
A. Nishikawa ◽  
N.I. Kato ◽  
J. Matsuzawa ◽  
K. Takagi ◽  
N. Miura
Keyword(s):  
Failure Analysis ◽  
Transient Behavior ◽  
Cross Sectional ◽  
Root Cause ◽  
Analysis Technique ◽  
Defect Isolation ◽  
Electron Image ◽  
Open Defects ◽  
Leakage Failure ◽  
Current Emission

Abstract A new analysis method using conventional emission microscopy (EMS) was developed for localizing open defects in CMOS LSIs. EMS is widely used for failure analysis of IDD (power supply current) leakage failures. The root cause of a failure is deduced by considering the emission characteristics associated with the IDD leakage current, emission shape, emission energy spectrum, and exact location on an Si die. Our new technique focuses on the observation of transient photoemission immediately after VDD application. During IDD leakage failure analysis, unique transient photoemission characteristics are observed. Immediately after VDD application, strong photoemission is briefly observed at the drain edge of an n-FET, but disappears after stabilization of the IDD current. We assumed that temporary photoemission would not be generated in transient behavior unless some kind of open defects were located at a specific conductor connected to the gate electrode. This mechanism was verified by nonbiased charge-up contrast of a conventional secondary electron image (SEI) and cross-sectional SEM observation at the defective open location. The dynamic method of observing transient photoemission proposed here is a very effective and practical way for detecting the locations of open failures in CMOS LSIs. Some examples of open mode failure analysis are described, along with cross-sectional TEM observations.

Characterization of Gate Oxide Pinhole Defect in NMOS FinFET Devices

2017 ◽  
Author(s):  
Liangshan Chen ◽  
Arnaud Bousquet ◽  
Tanya Schaeffer ◽  
Lucile C. Teague Sheridan ◽  
Lowell Hodgkins ◽  
...  
Keyword(s):  
Failure Mechanism ◽  
Electron Tomography ◽  
Gate Oxide ◽  
The Other ◽  
Physical Analysis ◽  
Tem Analysis ◽  
Root Cause ◽  
The Common ◽  
Tomography Analysis

Abstract This paper highlights the application of nanoprobing technique and electron tomography analysis to characterize the tiny gate oxide pinhole defect in NMOS FinFET devices. Nanoprobing technique was utilized to achieve a better understanding on the failure mechanism by characterizing the device electrical behaviors, and electron tomography, capable of mitigating the common projection issue encountered by general TEM analysis, was applied for physical analysis. It has been demonstrated through two cases, one logic fail and the other memory fail, that these two techniques together can effectively identify the root cause of pinhole defect. This type of pinhole defect, characterized by a tiny spot of oxide discontinuity and without excessive materials inter-diffusion, has been extremely challenging in FA analysis. This paper will provide the analysis details leading to the successful characterization of such type of oxide pinhole defect.

Failure Analysis Methodology on Systematic Defect in N+ poly/NWELL Varactor in RF Analog_PLL due to Implanter Charging Issue

2012 ◽  
Author(s):  
Ang Ghim Boon ◽  
Chen Changqing ◽  
Ng Hui Peng ◽  
Neo Soh Ping ◽  
Magdeliza G ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Gate Oxide ◽  
Oxide Breakdown ◽  
Root Cause ◽  
Path Tracing ◽  
Analysis Methodology ◽  
Problem Solving Process ◽  
Access To Data ◽  
Analog Circuitry

Abstract In this paper, a zero yield case relating to a systematic defect in N+ poly/N-well varactor (voltage controlled capacitor) on the RF analog circuitry will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging and nano-probing, manual layout path tracing, FIB circuit edit, selective etching together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical for a foundry company with restricted access to data on test condition setup to duplicate the exact failure as well as no layout tracing available at time of analysis. The systematic defect was due to gate oxide breakdown as a result of implanter charging. It serves as a good reference to other wafer Fabs encountering such an issue.

Unique Approaches to Isolate Nanoscale Defect in Snake-Comb Test Structure

2015 ◽  
Author(s):  
Sujing Xie ◽  
Nathan Wang ◽  
Chaoying Chen ◽  
Qindi Wu
Keyword(s):  
Failure Analysis ◽  
Electrical Resistance ◽  
Test Structure ◽  
Yield Enhancement ◽  
Nanometer Scale ◽  
Cross Sectional ◽  
Root Cause ◽  
Unique Approach ◽  
Voltage Contrast ◽  
Root Cause Identification

Abstract Multiple techniques including electrical resistance measurement plus calculation, cross-sectional view of passive voltage contrast (XPVC) sequential searching, planar and cross-section STEM are successfully used to isolate a nanoscale defect, single metallic stringer in a snakecomb test structure. The defect could not be found by traditional failure analysis methods or procedures. The unique approach presented here, expands failure analysis capabilities to the detection of nanometer-scale defects and the identification of their root causes. With continuous shrinking feature sizes, the need of such techniques becomes more vital to failure analysis and root cause identification, and therefore yield enhancement in fabrication.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Sign in / Sign up

Export Citation Format

Share Document