scholarly journals A NEW EXTRINSIC GETTERING TECHNIQUE IN THICK BONDED SILICON-ON-INSULATOR WAFERS ENABLING SENSOR-IC INTEGRATION

Author(s):  
P. Sandow ◽  
S. Whiston ◽  
P. Daly ◽  
J. Mäkinen ◽  
J. Hintsala ◽  
...  
Keyword(s):  
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.


Author(s):  
Frances M. Ross ◽  
Peter C. Searson

Porous semiconductors represent a relatively new class of materials formed by the selective etching of a single or polycrystalline substrate. Although porous silicon has received considerable attention due to its novel optical properties1, porous layers can be formed in other semiconductors such as GaAs and GaP. These materials are characterised by very high surface area and by electrical, optical and chemical properties that may differ considerably from bulk. The properties depend on the pore morphology, which can be controlled by adjusting the processing conditions and the dopant concentration. A number of novel structures can be fabricated using selective etching. For example, self-supporting membranes can be made by growing pores through a wafer, films with modulated pore structure can be fabricated by varying the applied potential during growth, composite structures can be prepared by depositing a second phase into the pores and silicon-on-insulator structures can be formed by oxidising a buried porous layer. In all these applications the ability to grow nanostructures controllably is critical.


Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.


Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions


Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.


Author(s):  
A. De Veirman ◽  
J. Van Landuyt ◽  
K.J. Reeson ◽  
R. Gwilliam ◽  
C. Jeynes ◽  
...  

In analogy to the formation of SIMOX (Separation by IMplanted OXygen) material which is presently the most promising silicon-on-insulator technology, high-dose ion implantation of cobalt in silicon is used to synthesise buried CoSi2 layers. So far, for high-dose ion implantation of Co in Si, only formation of CoSi2 is reported. In this paper it will be shown that CoSi inclusions occur when the stoichiometric Co concentration is exceeded at the peak of the Co distribution. 350 keV Co+ ions are implanted into (001) Si wafers to doses of 2, 4 and 7×l017 per cm2. During the implantation the wafer is kept at ≈ 550°C, using beam heating. The subsequent annealing treatment was performed in a conventional nitrogen flow furnace at 1000°C for 5 to 30 minutes (FA) or in a dual graphite strip annealer where isochronal 5s anneals at temperatures between 800°C and 1200°C (RTA) were performed. The implanted samples have been studied by means of Rutherford Backscattering Spectroscopy (RBS) and cross-section Transmission Electron Microscopy (XTEM).


2020 ◽  
Vol 23 (3) ◽  
pp. 227-252
Author(s):  
T.E. Rudenko ◽  
◽  
A.N. Nazarov ◽  
V.S. Lysenko ◽  
◽  
...  

Author(s):  
Yasunori Goto ◽  
Hiroomi Eguchi ◽  
Masaru Iida

Abstract In the automotive IC using thick-film silicon on insulator (SOI) semiconductor device, if the gettering capability of a SOI wafer is inadequate, electrical characteristics degradation by metal contamination arises and the yield falls. At this time, an automotive IC was made experimentally for evaluation of the gettering capability as one of the purposes. In this IC, one of the output characteristics varied from the standard, therefore failure analysis was performed, which found trace metal elements as one of the causes. By making full use of 3D perspective, it is possible to fabricate a site-specific sample into 0.1 micrometre in thickness without missing a failure point that has very minute quantities of contaminant in a semiconductor device. Using energy dispersive X-ray, it is possible to detect trace metal contamination at levels 1E12 atoms per sq cm. that are conventionally detected only by trace element analysis.


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