scholarly journals Nonvolatile Analog Switch for Low-Voltage Applications

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 736
Author(s):  
Giorgiana-Catalina Ilie (Chiranu) ◽  
Cristian Tudoran ◽  
Otilia Neagoe ◽  
Florin Draghici ◽  
Gheorghe Brezeanu
Keyword(s):  
Power Consumption ◽  
Gate Voltage ◽  
Low Voltage ◽  
Supply Voltage ◽  
Memory Cell ◽  
Floating Gate ◽  
Test Chip ◽  
Analog Switch ◽  
Input Source ◽  
State Resistance

In this paper, a nonvolatile switch based on n-type floating-gate transistors is described. The switch states are programmed through the memory cell floating-gate voltage, allowing higher levels than the application supply. Furthermore, due to its nonvolatile nature, the power consumption is reduced. The on-state resistance, which does not depend on the supply voltage, is one of the greatest advantages of this type of switch in comparison to conventional switches. This benefit can be successfully exploited in low-voltage applications. The switch on-resistance can be increased without the need for increasing the switch area. The characteristics of the proposed switch were confirmed by the experimental results obtained on a test chip fabricated in a 0.18 µm EEPROM process. Measured on-resistance values between 45 and 70 Ω were obtained for a floating-gate voltage of 6.2 V and input source levels below 2 V. The required programming voltage was 18 V. The maximum off-state leakage current was measured at 5 nA.

scholarly journals Ultra-Low-Voltage Low-Power Bulk-Driven Quasi-Floating-Gate Operational Transconductance Amplifier

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Ziad Alsibai ◽  
Salma Bay Abo Dabbous
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Bias Current ◽  
Floating Gate ◽  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier

A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.

ULTRA-LOW VOLTAGE TUNABLE TRANSCONDUCTOR BASED ON BULK-DRIVEN QUASI-FLOATING-GATE TECHNIQUE

2013 ◽  
Vol 22 (08) ◽  
pp. 1350073 ◽  
Author(s):  
FABIAN KHATEB ◽  
NABHAN KHATIB ◽  
PIPAT PROMMEE ◽  
WINAI JAIKLA ◽  
LUKAS FUJCIK
Keyword(s):  
Power Consumption ◽  
Low Voltage ◽  
Supply Voltage ◽  
Floating Gate ◽  
Low Power Consumption ◽  
Mos Transistor ◽  
External Resistor ◽  
Multifunction Filter ◽  
Simulation Results ◽  
Low Supply Voltage

This paper presents ultra-low voltage transconductor using a new bulk-driven quasi-floating-gate technique (BD-QFG). This technique leads to significant increase in the transconductance and the bandwidth values of the MOS transistor (MOST) under ultra-low voltage condition. The proposed CMOS structure of the transconductor is capable to work with ultra-low supply voltage of ±300 mV and low power consumption of 18 μW. The transconductance value of the transconductor is tunable by external resistor with wide linear range. To prove the validation of the new described technique a second-order Gm-C multifunction filter is presented as one of the possible applications. The simulation results using 0.18 μm CMOS N-Well process from TSMC show the attractive features of the proposed circuit.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

Low Voltage FGMOS Four Quadrants Analog Multiplier

2014 ◽  
Vol 918 ◽  
pp. 313-318
Author(s):  
Jesús de la Cruz-Alejo ◽  
L. Noe Oliva-Moreno
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Low Voltage ◽  
Floating Gate ◽  
Cmos Process ◽  
Resistive Load ◽  
Analog Multiplier ◽  
Output Impedance ◽  
Cmos Transistors ◽  
Current Sensors

In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

TUNABLE ACTIVE FILTERS FOR RF AND MICROWAVE APPLICATIONS

2014 ◽  
Vol 23 (06) ◽  
pp. 1450088 ◽  
Author(s):  
LEONARDO PANTOLI ◽  
VINCENZO STORNELLI ◽  
GIORGIO LEUZZI
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Bandpass Filter ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Active Filters ◽  
Center Frequency ◽  
Power Supply Voltage ◽  
Microwave Applications

In this paper, we present a low-voltage tunable active filter for microwave applications. The proposed filter is based on a single-transistor active inductor (AI), that allows the reduction of circuit area and power consumption. The three active-cell bandpass filter has a 1950 MHz center frequency with a -1 dB flat bandwidth of 10 MHz (Q ≈ 200), a shape factor (30–3 dB) of 2.5, and can be tuned in the range 1800–2050 MHz, with constant insertion loss. A dynamic range of about 75 dB is obtained, with a P1dB compression point of -5 dBm. The prototype board, fabricated on a TLX-8 substrate, has a 4 mW power consumption with a 1.2 V power supply voltage.

scholarly journals Low-Power High-Speed Double Gate 1-bit Full Adder Cell

2016 ◽  
Vol 62 (4) ◽  
pp. 329-334 ◽  
Author(s):  
Raushan Kumar ◽  
Sahadev Roy ◽  
C.T. Bhunia
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Spice Simulation ◽  
Pass Transistor ◽  
Voltage Swing

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

2015 ◽  
Vol 19 ◽  
pp. 19-36 ◽  
Author(s):  
P.A. Gowri Sankar ◽  
G. Sathiyabama
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Field Effect ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Flash Adc ◽  
Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

scholarly journals Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Maneesha Gupta ◽  
Richa Srivastava ◽  
Urvashi Singh
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Order Effect ◽  
Floating Gate ◽  
Current Output ◽  
Mos Transistor ◽  
Differential Voltage ◽  
Saturation Region ◽  
Linear Differential ◽  
Low Supply Voltage

This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

scholarly journals Study on Cross-Coupled-Based Sensing Circuits for Nonvolatile Flip-Flops Operating in Near/Subthreshold Voltage Region

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1177
Author(s):  
Taehui Na
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Test Chip ◽  
Offset Voltage ◽  
Higher Power ◽  
Measurement Results ◽  
Subthreshold Voltage ◽  
The Cost ◽  
Voltage Region

To date, most studies focus on complex designs to realize offset cancelation characteristics in nonvolatile flip-flops (NV-FFs). However, complex designs using switches are ineffective for offset cancelation in the near/subthreshold voltage region because switches become critical contributors to the offset voltage. To address this problem, this paper proposes a novel cross-coupled NMOS-based sensing circuit (CCN-SC) capable of improving the restore yield, based on the concept that the simplest is the best, of an NV-FF operating in the near/subthreshold voltage region. Measurement results using a 65 nm test chip demonstrate that with the proposed CCN-SC, the restore yield is increased by more than 25 times at a supply voltage of 0.35 V, compared to that with a cross-coupled inverter-based SC, at the cost of 18× higher power consumption.

High Stable and Low Power 10T CNTFET SRAM Cell

2019 ◽  
Vol 29 (10) ◽  
pp. 2050158
Author(s):  
M. Elangovan ◽  
K. Gunavathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Large Scale ◽  
Supply Voltage ◽  
Memory Cell ◽  
Vlsi Circuits ◽  
Order Effects ◽  
Power Performance ◽  
Sram Cell ◽  
Nanoscale Range

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

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