scholarly journals Effect of Bonding Strength on Electromigration Failure in Cu–Cu Bumps

Materials ◽  
2021 ◽  
Vol 14 (21) ◽  
pp. 6394
Author(s):  
Kai-Cheng Shie ◽  
Po-Ning Hsu ◽  
Yu-Jin Li ◽  
K. N. Tu ◽  
Chih Chen
Keyword(s):  
Integrated Circuits ◽  
Current Density ◽  
Contact Area ◽  
Bonding Strength ◽  
Three Dimensional ◽  
Open Circuit ◽  
Current Crowding ◽  
Early Failure ◽  
Bonding Structure ◽  
Diffusion Paths

In microelectronic packaging technology for three-dimensional integrated circuits (3D ICs), Cu-to-Cu direct bonding appears to be the solution to solve the problems of Joule heating and electromigration (EM) in solder microbumps under 10 μm in diameter. However, EM will occur in Cu–Cu bumps when the current density is over 106 A/cm2. The surface, grain boundary, and the interface between the Cu and TiW adhesion layer are the three major diffusion paths in EM tests, and which one may lead to early failure is of interest. This study showed that bonding strength affects the outcome. First, if the bonding strength is not strong enough to sustain the thermal mismatch of materials during EM tests, the bonding interface will fracture and lead to an open circuit of early failure. Second, if the bonding strength can sustain the bonding structure, voids will form at the passivation contact area between the Cu–Cu bump and redistribution layer (RDL) due to current crowding. When the void grows along the passivation interface and separates the Cu–Cu bump and RDL, an open circuit can occur, especially when the current density and temperature are severe. Third, under excellent bonding, when the voids at the contact area between the Cu–Cu bump and RDL do not merge together, the EM lifetime can be more than 5000 h.

The Influence of Skin Effect on Via-Vicinity-Interfaces Current Density of Cu Interconnects

2012 ◽  
Vol 548 ◽  
pp. 551-554
Author(s):  
Ming Yao ◽  
Xu Liang Zhang
Keyword(s):  
Current Density ◽  
Skin Effect ◽  
Ground Plane ◽  
Three Dimensional ◽  
Current Density Distribution ◽  
Copper Interconnects ◽  
Current Crowding ◽  
Cu Interconnects ◽  
Surface Areas ◽  
Cu Interconnect

This paper presents a research on skin effect’s influence on the current density distribution of Cu/barrier layer and Cu/cap layer interfaces of copper interconnects’ via vicinities. A two-level Cu-interconnect structure in different positional relationships with the ground plane is discussed. Through the three-dimensional (3D) finite element simulation of the interconnect structure, the variations of current density on three important surface areas are obtained when skin effect is significant, showing that the current density in the three surface areas near the via has been strongly influenced by current crowding and skin effect. So in many cases the influence of skin effect on via top and via bottom failures of Cu interconnects under high frequencies can not be ignored.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Analytical electron microscopy of grain boundaries in Al-Cu metallizations

1992 ◽  
Vol 50 (2) ◽  
pp. 1684-1685
Author(s):  
J. R. Michael ◽  
A. D. Romig ◽  
D. R. Frear
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Failure Mode ◽  
Current Density ◽  
Thermal History ◽  
Analytical Electron Microscopy ◽  
Cu Metallization ◽  
Analytical Electron ◽  
Interconnect Lines

Al with additions of Cu is commonly used as the conductor metallizations for integrated circuits, the Cu being added since it improves resistance to electromigration failure. As linewidths decrease to submicrometer dimensions, the current density carried by the interconnect increases dramatically and the probability of electromigration failure increases. To increase the robustness of the interconnect lines to this failure mode, an understanding of the mechanism by which Cu improves resistance to electromigration is needed. A number of theories have been proposed to account for role of Cu on electromigration behavior and many of the theories are dependent of the elemental Cu distribution in the interconnect line. However, there is an incomplete understanding of the distribution of Cu within the Al interconnect as a function of thermal history. In order to understand the role of Cu in reducing electromigration failures better, it is important to characterize the Cu distribution within the microstructure of the Al-Cu metallization.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

scholarly journals Fabrication of Eutectic Ga-In Nanowire Arrays Based on Plateau–Rayleigh Instability

Molecules ◽  
2021 ◽  
Vol 26 (15) ◽  
pp. 4616
Author(s):  
Takashi Ikuno ◽  
Zen Somei
Keyword(s):  
Integrated Circuits ◽  
Substrate Surface ◽  
Three Dimensional ◽  
Average Diameter ◽  
Nanowire Arrays ◽  
Scanning Probe ◽  
Rayleigh Instability ◽  
Simple Method ◽  
Flat Substrate ◽  
Metal Nanowire

We have developed a simple method of fabricating liquid metal nanowire (NW) arrays of eutectic GaIn (EGaIn). When an EGaIn droplet anchored on a flat substrate is pulled perpendicular to the substrate surface at room temperature, an hourglass shaped EGaIn is formed. At the neck of the shape, based on the Plateau–Rayleigh instability, the EGaIn bridge with periodically varying thicknesses is formed. Finally, the bridge is broken down by additional pulling. Then, EGaIn NW is formed at the surface of the breakpoint. In addition, EGaIn NW arrays are found to be fabricated by pulling multiple EGaIn droplets on a substrate simultaneously. The average diameter of the obtained NW was approximately 0.6 μm and the length of the NW depended on the amount of droplet anchored on the substrate. The EGaIn NWs fabricated in this study may be used for three-dimensional wiring for integrated circuits, the tips of scanning probe microscopes, and field electron emission arrays.

Thermomechanical Coupling of a Hyper-viscoelastic Truck Tire and a Pavement Layer and its Impact on Three-dimensional Contact Stresses

2021 ◽  
pp. 036119812110171
Author(s):  
Angeli Jayme ◽  
Imad L. Al-Qadi
Keyword(s):  
Contact Stress ◽  
Contact Area ◽  
Three Dimensional ◽  
Interaction Model ◽  
Rolling Resistance ◽  
Contact Stresses ◽  
Thermomechanical Coupling ◽  
Temperature Profiles ◽  
Near Surface ◽  
Truck Tire

A thermomechanical coupling between a hyper-viscoelastic tire and a representative pavement layer was conducted to assess the effect of various temperature profiles on the mechanical behavior of a rolling truck tire. The two deformable bodies, namely the tire and pavement layer, were subjected to steady-state-uniform and non-uniform temperature profiles to identify the significance of considering temperature as a variable in contact-stress prediction. A myriad of ambient, internal air, and pavement-surface conditions were simulated, along with combinations of applied tire load, tire-inflation pressure, and traveling speed. Analogous to winter, the low temperature profiles induced a smaller tire-pavement contact area that resulted in stress localization. On the other hand, under high temperature conditions during the summer, higher tire deformation resulted in lower contact-stress magnitudes owing to an increase in the tire-pavement contact area. In both conditions, vertical and longitudinal contact stresses are impacted, while transverse contact stresses are relatively less affected. This behavior, however, may change under a non-free-rolling condition, such as braking, accelerating, and cornering. By incorporating temperature into the tire-pavement interaction model, changes in the magnitude and distribution of the three-dimensional contact stresses were manifested. This would have a direct implication on the rolling resistance and near-surface behavior of flexible pavements.

Three-dimensional porous copper-decorated bismuth-based nanofoam for boosting electrochemical reduction of CO2 to formate

2021 ◽  
Author(s):  
Yingchun Zhang ◽  
Changsheng Cao ◽  
Xintao Wu ◽  
Qi-Long Zhu
Keyword(s):  
Current Density ◽  
High Current Density ◽  
Three Dimensional ◽  
Co2 Reduction ◽  
Reduction Reaction ◽  
High Current ◽  
Porous Copper ◽  
Reduction Of Co2 ◽  
Co2 Reduction Reaction ◽  
Wide Potential

Bismuth (Bi)-based nanomaterials are considered as the promising electrocatalysts for electrocatalytic CO2 reduction reaction (CO2RR), but it is challenging to achieve high current density and selectivity in a wide potential...

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

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