scholarly journals A New Current-Shaping Technique Based on a Feedback Injection Mechanism to Reduce VCO Phase Noise

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6583
Author(s):  
Francisco Javier del Pino Suárez ◽  
Sunil Lalchand Khemchandani
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Chip Area ◽  
Load Variations ◽  
Voltage Controlled Oscillators ◽  
Radar Sensors ◽  
Low Area ◽  
Injection Mechanism

Inductor-capacitor voltage controlled oscillators (LC-VCOs) are the most common type of oscillator used in sensors systems, such as transceivers for wireless sensor networks (WSNs), VCO-based reading circuits, VCO-based radar sensors, etc. This work presents a technique to reduce the LC-VCOs phase noise using a new current-shaping method based on a feedback injection mechanism with only two additional transistors. This technique consists of keeping the negative resistance seen from LC tank constant throughout the oscillation cycle, achieving a significant phase noise reduction with a very low area increase. To test this method an LC-VCO was designed, fabricated and measured on a wafer using 90 nm CMOS technology with 1.2 V supply voltage. The oscillator outputs were buffered using source followers to provide additional isolation from load variations and to boost the output power. The tank was tuned to 1.8 GHz, comprising two 1.15 nH with 1.5 turns inductors with a quality factor (Q) of 14, a 3.27 pF metal-oxide-metal capacitor, and two varactors. The measured phase noise was −112 dBc/Hz at 1 MHz offset. Including the pads, the chip area is 750 × 850 μm2.

Low Phase Noise and Low Power Voltage-Controlled-Oscillator Using Current-Reuse Techniques for Wireless Communication Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 1010-1013
Author(s):  
Tsung Han Han ◽  
Meng Ting Hsu ◽  
Cheng Chuan Chung
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Voltage Controlled Oscillators ◽  
Communication Circuits ◽  
5 Ghz ◽  
Low Phase Noise

In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18 μm CMOS process. The designed circuit topology is included a current-reused configuration. It is adopted memory-reduced tail transistor technique. At the supply voltage 1.5 v, the measured output phase noise is-116.071 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.2 GHz. The core power consumption is 3.7 mW, and tuning range of frequency is about 1.3 GHz from 4.8 to 6.1 GHz. The chip area is 826.19 × 647.83 um2.

Design of a Low-Phase-Noise LC Voltage Controlled Oscillator

2014 ◽  
Vol 519-520 ◽  
pp. 1095-1098
Author(s):  
Cheng Hong Dong ◽  
Chang Chun Zhang ◽  
Yu Feng Guo ◽  
Lei Lei Liu ◽  
Xin Cun Ji ◽  
...  
Keyword(s):  
Phase Noise ◽  
Figure Of Merit ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Voltage Controlled Oscillator ◽  
Frequency Range ◽  
Supply Current ◽  
Low Phase Noise ◽  
Lc Vco

A novel low phase noise LC Voltage Controlled Oscillator (LC-VCO) is designed in standard 0.18μm CMOS technology. Instead of common NMOS cross-pairs for a conventional complementary LC VCO, both body-biasing and Q-enhancement techniques are employed to provide a larger negative resistance for the VCO. Post-layout simulations showed that it can oscillate at a frequency range of 4.34-4.73GHz, and comsume a supply current of 1.52mA from a supply voltage of 1.8V. The VCO achieves a phase noise of -132.8dBc/Hz @ 1MHz offset and a figure of merit (FOM) of -195.9dBc/Hz at the frequency of 4.5GHz. A die area of 475μm×498.6μm is occupied.

scholarly journals Receiver Designs for Electronic Toll Collection Systems : A Survey

2020 ◽  
pp. 576-581
Author(s):  
Rarika Ravi ◽  
Anu Assis
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Power Level ◽  
Cmos Technology ◽  
Electronic Toll Collection ◽  
Chip Area ◽  
Advantages And Disadvantages ◽  
Digitally Controlled ◽  
Toll Collection

<p>This paper discusses about different receiver designs adopted so far for various electronic toll collection systems. A comparative analysis based on the discussions is also provided. It shows that each design has it's own advantages and disadvantages compared to others. The main aim of this paper is to identify the most suitable design. The researches shows that the receiver design described in the 5.8GHz digitally controlled DSRC receiver for Chinese electronic toll collection system is the most suitable one. Here all RF, IF blocks and digital baseband for on-chip automatic gain control, are integrated on an RF-SoC. The proposed digitally controlled LNA and mixer circuits are elaborated. The technology used is 0.13μm CMOS technology. The RF block occupies a chip area of 0.75mm2. It consumes 22mA under a 1.5V supply voltage. The bit error rate maintains better than 10-6, the input power level varies from -75dBm to -8dBm. This design provides a receiver sensitivity improvement of at least 25%, and a dynamic range enhancement of at least 12%.</p>

A CMOS Automatic Gain Control Circuit for Biomedical Applications

2015 ◽  
Vol 645-646 ◽  
pp. 1308-1313
Author(s):  
Zhi Qiang Gao ◽  
Fu Xiang Huang ◽  
Jing Li ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Exponential Function ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Cmos Technology ◽  
Chip Area ◽  
Gain Variation ◽  
Linearity Error

In this paper, a low-voltage automatic gain control (AGC) circuits is presented. The proposed circuit uses a novel approximated exponential function to increase the dB-linear output range. The three-stage AGC is fabricated in 0.18μm CMOS technology and shows the maximum gain variation of more than 100dB and a 67dB linear range with linearity error of less than ±1dB. The range of gain variation can be controlled from 34 to 101dB. The AGC dissipates less than 2.3mA under 1.8V supply voltage while occupying 0.4mm2 of chip area.

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chip Area ◽  
Active Inductors ◽  
Low Pass ◽  
Optical Applications ◽  
Fifth Order

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

scholarly journals A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Chip Area ◽  
Loop Bandwidth ◽  
Bandwidth Control ◽  
Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

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