scholarly journals Hybrid self-controlled precharge-free CAM design for low power and high performance

2019 ◽  
pp. 1132-1146
Author(s):  
V V SATYANARAYANA SATTI ◽  
SRIDEVI SRIADIBHATLA
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Charge Sharing ◽  
Content Addressable Memory ◽  
Current Path ◽  
High Power Consumption

Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consumes larger power. Traditional NOR and NAND match-line (ML) architectures suffer from a short circuit current path sharing and charge sharing respectively during precharge. The recently proposed precharge-free CAM suffers from high search delay and the subsequently proposed self-controlled precharge-free CAM suffers from high power consumption. This paper presents a hybrid self-controlled precharge-free (HSCPF) CAM architecture, which uses a novel charge control circuitry to reduce search delay as well as power consumption. The proposed and existing CAM ML architectures were developed using CMOS 45nm technology node with a supply voltage of 1 V. Simulation results show that the proposed HSCPF CAM-type ML design reduces power consumption and search delay effectively when compared to recent precharge-free CAM-type ML architectural designs.

scholarly journals Ultra high speed full adder for biomedical applications

2021 ◽  
Vol 10 (1) ◽  
pp. 25
Author(s):  
Basavoju Harish ◽  
M. S. S. Rukmini
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Medical Engineering ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Devices ◽  
Ripple Carry Adder ◽  
Power Delay Product

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption

2015 ◽  
Vol 24 (10) ◽  
pp. 1550159 ◽  
Author(s):  
Ramin Razmdideh ◽  
Ali Mahani ◽  
Mohsen Saneei
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Switching Activity ◽  
Flip Flop ◽  
Reduce Power Consumption ◽  
Controlled Switching ◽  
Simulation Results

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

scholarly journals Low Power High Speed Ternary Content Addressable Memory

2019 ◽  
Vol 8 (2) ◽  
pp. 2454-2458
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Search Engine ◽  
High Speed ◽  
Supply Voltage ◽  
Content Addressable Memory ◽  
Ternary Content Addressable Memory

Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V.

scholarly journals A Novel Low Voltage Selective Circuit Breaker with Additional Current Path

Energies ◽  
2021 ◽  
Vol 14 (23) ◽  
pp. 8179
Author(s):  
Bartosz Rozegnał ◽  
Paweł Albrechtowicz ◽  
Piotr Cisek
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Short Circuit ◽  
Circuit Breaker ◽  
Short Circuit Current ◽  
Circuit Breakers ◽  
Current Path ◽  
Correct Reaction ◽  
The Subject ◽  
Selection Of

The subject of the article is a description of the operating principle of the new proposal of the selective circuit breaker, which is an extension of the existing selective devices. The solution proposed in the article allows one to increase the selectivity range of classic selective circuit breakers. In the case of networks with high values of short-circuit loop impedance, operating at reduced supply voltage, the proposed solution will not limit the short-circuit current too excessively as it is in the case of classic solutions. This advantage will allow for the correct reaction of the protections preceding them. The article presents the structure and analysis of the selection of parameters of the proposed solution. The results of simulation calculations have also been illustrated.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

scholarly journals Antireflection Improvement and Junction Quality Optimization of Si/PEDOT:PSS Solar Cell with the Introduction of Dopamine@Graphene

Energies ◽  
2020 ◽  
Vol 13 (22) ◽  
pp. 5986
Author(s):  
Tao Chen ◽  
Hao Guo ◽  
Leiming Yu ◽  
Tao Sun ◽  
Anran Chen ◽  
...  
Keyword(s):  
Solar Cell ◽  
Conversion Efficiency ◽  
High Performance ◽  
Electrochemical Impedance ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Electrochemical Impedance Spectra ◽  
Solar Cell Performance ◽  
Photovoltaic Conversion ◽  
Photovoltaic Conversion Efficiency

Si/PEDOT: PSS solar cell is an optional photovoltaic device owing to its promising high photovoltaic conversion efficiency (PCE) and economic manufacture process. In this work, dopamine@graphene was firstly introduced between the silicon substrate and PEDOT:PSS film for Si/PEDOT: PSS solar cell. The dopamine@graphene was proved to be effective in improving the PCE, and the influence of mechanical properties of dopamine@graphene on solar cell performance was revealed. When dopamine@graphene was incorporated into the cell preparation, the antireflection ability of the cell was enhanced within the wavelength range of 300~450 and 650~1100 nm. The enhanced antireflection ability would benefit amount of the photon-generated carriers. The electrochemical impedance spectra test revealed that the introduction of dopamine@graphene could facilitate the separation of carriers and improve the junction quality. Thus, the short-circuit current density and fill factor were both promoted, which led to the improved PCE. Meanwhile, the influence of graphene concentration on device performances was also investigated. The photovoltaic conversion efficiency would be promoted from 11.06% to 13.15% when dopamine@graphene solution with concentration 1.5 mg/mL was applied. The achievements of this study showed that the dopamine@graphene composites could be an useful materials for high-performance Si/PEDOT:PSS solar cells.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals A Self-Powered Nanogenerator for the Electrical Protection of Integrated Circuits from Trace Amounts of Liquid

2019 ◽  
Vol 12 (1) ◽  
Author(s):  
Zhuang Hui ◽  
Ming Xiao ◽  
Daozhi Shen ◽  
Jiayun Feng ◽  
Peng Peng ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Printed Circuit Board ◽  
Short Circuit ◽  
High Sensitivity ◽  
Short Circuit Current ◽  
Fast Response ◽  
Open Circuit ◽  
Circuit Board ◽  
Self Powered

Abstract With the increase in the use of electronic devices in many different environments, a need has arisen for an easily implemented method for the rapid, sensitive detection of liquids in the vicinity of electronic components. In this work, a high-performance power generator that combines carbon nanoparticles and TiO2 nanowires has been fabricated by sequential electrophoretic deposition (EPD). The open-circuit voltage and short-circuit current of a single generator are found to exceed 0.7 V and 100 μA when 6 μL of water was applied. The generator is also found to have a stable and reproducible response to other liquids. An output voltage of 0.3 V was obtained after 244, 876, 931, and 184 μs, on exposure of the generator to 6 μL of water, ethanol, acetone, and methanol, respectively. The fast response time and high sensitivity to liquids show that the device has great potential for the detection of small quantities of liquid. In addition, the simple easily implemented sequential EPD method ensures the high mechanical strength of the device. This compact, reliable device provides a new method for the sensitive, rapid detection of extraneous liquids before they can impact the performance of electronic circuits, particularly those on printed circuit board.

Fluttering Amplitude Amplification by Utilizing Flapping Moment in Flutter-Driven Triboelectric Nanogenerator

2021 ◽  
Author(s):  
Yi Zhang ◽  
Ka Chung Chan ◽  
Sau Chung Fu ◽  
Christopher Yu Hang Chao
Keyword(s):  
Flow Velocity ◽  
High Speed ◽  
Aerodynamic Force ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Open Circuit ◽  
Energy Output ◽  
Small Scale ◽  
Triboelectric Nanogenerator ◽  
Peak Value

Abstract Flutter-driven triboelectric nanogenerator (FTENG) is one of the most promising methods to harvest small-scale wind energy. Wind causes self-fluttering motion of a flag in the FTENG to generate electricity by contact electrification. A lot of studies have been conducted to enhance the energy output by increasing the surface charge density of the flag, but only a few researches tried to increase the converting efficiency by enlarging the flapping motion. In this study, we show that by simply replacing the rigid flagpole in the FTENG with a flexible flagpole, the energy conversion efficiency is augmented and the energy output is enhanced. It is found that when the flag flutters, the flagpole also undergoes aerodynamic force. The lift force generated from the fluttering flag applies a periodic rotational moment on the flagpole, and causes the flagpole to vibrate. The vibration of the flagpole, in turn amplifies the flutter of the flag. Both the fluttering dynamics of the flags with rigid and flexible flagpoles have been recorded by a high-speed camera. When the flag was held by a flexible flagpole, the fluttering amplitude and the contact area between the flag and electrode plates were increased. The energy enhancement increased as the flow velocity increased and the enhancement can be 113 times when the wind velocity is 10 m/s. The thickness of the flagpole was investigated. An optimal output of open-circuit voltage reaching 1128 V (peak-to-peak value) or 312.40 V (RMS value), and short-circuit current reaching 127.67 μA (peak-to-peak value) or 31.99 μA (RMS value) at 12.21 m/s flow velocity was achieved. This research presents a simple design to enhance the output performance of an FTENG by amplifying the fluttering amplitude. Based on the performance obtained in this study, the improved FTENG has the potential to apply in a smart city for driving electronic devices as a power source for IoT applications.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

Sign in / Sign up

Export Citation Format

Share Document