Performance of Surface Carrier Mobility for Nano-Node Strained (110) MOSFETs with Temperature Effect

2011 ◽  
Vol 291-294 ◽  
pp. 3131-3134
Author(s):  
Mu Chun Wang ◽  
Hsin Chia Yang ◽  
Wen Shiang Liao
Keyword(s):  
Mass Production ◽  
Carrier Mobility ◽  
Room Temperature ◽  
Phonon Scattering ◽  
Short Channel ◽  
Channel Mobility ◽  
Temperature Impact ◽  
Control Devices ◽  
And Control ◽  
Long Channel

Considering the increase of the driving current for nano-node MOSFET devices, source/drain (S/D) site etched and refilled with SiGe material is a promising process to promote the channel mobility due to the tensile or compressive effect. Using SiGe-S/D process comparing the performance with Si-S/D and control devices on (110) wafer to probe the nano-scale mass-production possibility is a good integration. Besides the discussion in the room temperature, the device characteristics with temperature dependence are more impressive. Through analysis for the cumulated data, the temperature impact in the performance of long channel MOSFETs is higher than that in the short channel ones. The phenomena can be attributed to the tensile or compressive effect to n- or p-MOSFETs with phonon scattering disturbance.

Comparison of channel mobility and oxide properties of MOSFET devices on Si-face (0001) and A-face (11-20) 4H-SiC

2014 ◽  
Vol 1693 ◽  
Author(s):  
Daniel J. Lichtenwalner ◽  
Lin Cheng ◽  
Scott Allen ◽  
John W. Palmour ◽  
Aivars Lelis ◽  
...  
Keyword(s):  
Valence Band ◽  
Barrier Height ◽  
Field Effect ◽  
Phonon Scattering ◽  
Electron Tunneling ◽  
Negative Temperature ◽  
Field Effect Mobility ◽  
Channel Mobility ◽  
P Type ◽  
And Control

ABSTRACTIn this report we present results comparing lateral MOSFET properties of devices fabricated on Si-face (0001) and A-face (11-20) 4H-SiC, with nitric oxide passivation anneals. We observe a field-effect mobility of 33 cm2/V.s on p-type 5×1015 doped Si-face. These devices have a peak field-effect mobility which increases with temperature, indicative of a channel mobility limited by coulomb scattering. On 1×1016 p-type A-face SiC, the peak channel mobility is observed to be 80 cm2/V.s, with a negative temperature dependence, indicating that phonon-scattering effects dominate, with a much lower density of shallow acceptor traps. This > 2x higher channel mobility would result in a substantial decrease in on-resistance, hence lower power losses, for 4H-SiC power MOSFETs with voltage ratings below 2 kV. However, MOS C-V and gate leakage measurements indicate very different oxide and interface quality on each SiC face. For example, the Fowler-Nordheim (FN) conduction-band (CB) barrier height for electron tunneling at the SiO2/SiC interface is 2.8 eV on Si-face SiC, while it is 2.5 eV or less on A-face SiC. For the valence-band side, the effective FN barrier height at the valence-band (VB) side of only 1.6 eV on A-face SiC, while the VB barrier height is about 3.1 eV on Si-face SiC. Moreover, C-V of the MOS gate on A-face indicates the presence of a high-density of deep hole traps. It is apparent that oxides on alternative crystal faces, very promising in terms of channel mobility, require further study for complete understanding and control of the interface properties.

scholarly journals Prediction of higher thermoelectric performance in BiOCuSe by weakening electron-polar optical phonon scattering

2020 ◽  
Author(s):  
Tianqi Zhao ◽  
Quinn Gibson ◽  
Luke Daniels ◽  
Ben Slater ◽  
Furio Cora
Keyword(s):  
Carrier Mobility ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Phonon Scattering ◽  
Hole Mobility ◽  
Polar Optical Phonon ◽  
First Principles Calculations ◽  
Thermoelectric Figure ◽  
Optical Phonon Scattering ◽  
Electron Phonon Scattering

Abstract BiOCuSe is a promising thermoelectric material, but its applications are hindered by low carrier mobility. We use first principles calculations to analyse electron-phonon scattering mechanisms and evaluate their contributions to the thermoelectric figure of merit ZT. The combined scattering of carriers by polar optical (PO) and longitudinal acoustic (LA) phonons yields an intrinsic hole mobility of 32 cm2 V-1 s-1 at room temperature and a temperature power law of T-1.5, which agree well with experiments. We demonstrate that electron phonon scattering in the Cu-Se layer dominates at low T, while contributions from the Bi-O layer become increasingly significant at higher T. At room temperature, ZT is calculated to be 0.48 and can be improved by 30% through weakening PO phonon scattering in the Cu-Se layer. This finding agrees with the experimental observation that weakening the carrier-phonon interaction by Te substitution in the Cu-Se layer improves mobility and ZT. At high T, the figure of merit is improved by weakening phonon scattering in the Bi-O layer instead. The theoretical ZT limit of BiOCuSe is calculated to be 2.5 at 875 K.

scholarly journals Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

2015 ◽  
Vol 2015 ◽  
pp. 1-5
Author(s):  
Avi Karsenty ◽  
Avraham Chelly
Keyword(s):  
Low Temperature ◽  
Potential Barrier ◽  
Room Temperature ◽  
Short Channel ◽  
Anomalous Effect ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Thickness ◽  
Recessed Channel ◽  
Long Channel

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

Improved Channel Mobility by Oxide Nitridation for N-Channel MOSFET on 3C-SiC(100)/Si

2016 ◽  
Vol 858 ◽  
pp. 667-670 ◽  
Author(s):  
Fan Li ◽  
Yogesh K. Sharma ◽  
M.R. Jennings ◽  
A. Pérez-Tomás ◽  
Vishal Ajit Shah ◽  
...  
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Oxidation Temperature ◽  
Channel Mobility ◽  
Si Substrates ◽  
Nitridation Process ◽  
Long Channel

In this work we studied the gate oxidation temperature and nitridation influences on the resultant 3C-SiC MOSFET forward characteristics. Conventional long channel lateral MOSFETs were fabricated on 3C-SiC(100) epilayers grown on Si substrates using five different oxidation process. Both room temperature and high temperature (up to 500K) forward IV performance were characterised, and channel mobility as high as 90cm2/V.s was obtained for devices with nitrided gate oxide, considerable higher than the ones without nitridation process (~70 cm2/V.s).

Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

2009 ◽  
Vol 1194 ◽  
Author(s):  
Dechao Guo ◽  
Kathryn Schonenberg ◽  
Jie Chen ◽  
Daniel Jaeger ◽  
Pranita Kulkarni ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Carrier Mobility ◽  
Metal Gate ◽  
Short Channel ◽  
Drive Current ◽  
Channel Mobility ◽  
Technology Node ◽  
Channel Control ◽  
First Time

AbstractFor the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

Modeling and Investigation of SiGe Based MOSFET Structure Transport Characteristics

2007 ◽  
Vol 555 ◽  
pp. 101-106
Author(s):  
P.M. Lukić ◽  
R.M. Ramović ◽  
Rajko M. Šašić
Keyword(s):  
Electric Field ◽  
Carrier Mobility ◽  
Mobility Model ◽  
Channel Length ◽  
Operating Characteristics ◽  
Short Channel ◽  
Electric Field Effects ◽  
Vertical Electric Field ◽  
Source Resistance ◽  
Long Channel

The focus of this paper was the investigation and modeling of transport characteristics in a strained SiGe based MOSFET structure, which might be of fundamental importance for the understanding of its operating characteristics. In the investigation, carrier mobility dependence on the lateral and vertical electric field is especially considered. Carrier mobility models for long channel as well as short channel SiGe MOSFETs are also presented. Average effective electric field model is proposed taking into account impact of high electric field effects on the effective channel length. In the final effective carrier mobility model, for the short channel SiGe MOSFETs, serial drain to source resistance is included. At the same time, proposed models are relatively simple. By using the presented model, simulations were performed.

Investigation of irradiation-induced nucleation processes in silicon and germanium

1995 ◽  
Vol 53 ◽  
pp. 224-225
Author(s):  
Harry A. Atwater ◽  
C.M. Yang ◽  
K.V. Shcheglov
Keyword(s):  
Room Temperature ◽  
Crystal Size ◽  
Initial Distribution ◽  
Engineering Control ◽  
Size Evolution ◽  
Silicon And Germanium ◽  
Ge Quantum Dot ◽  
And Control ◽  
Germanium Quantum Dots ◽  
Kinetics Of

Studies of the initial stages of nucleation of silicon and germanium have yielded insights that point the way to achievement of engineering control over crystal size evolution at the nanometer scale. In addition to their importance in understanding fundamental issues in nucleation, these studies are relevant to efforts to (i) control the size distributions of silicon and germanium “quantum dots𠇍, which will in turn enable control of the optical properties of these materials, (ii) and control the kinetics of crystallization of amorphous silicon and germanium films on amorphous insulating substrates so as to, e.g., produce crystalline grains of essentially arbitrary size.Ge quantum dot nanocrystals with average sizes between 2 nm and 9 nm were formed by room temperature ion implantation into SiO2, followed by precipitation during thermal anneals at temperatures between 30°C and 1200°C[1]. Surprisingly, it was found that Ge nanocrystal nucleation occurs at room temperature as shown in Fig. 1, and that subsequent microstructural evolution occurred via coarsening of the initial distribution.

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