Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

2009 ◽  
Vol 1194 ◽  
Author(s):  
Dechao Guo ◽  
Kathryn Schonenberg ◽  
Jie Chen ◽  
Daniel Jaeger ◽  
Pranita Kulkarni ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Carrier Mobility ◽  
Metal Gate ◽  
Short Channel ◽  
Drive Current ◽  
Channel Mobility ◽  
Technology Node ◽  
Channel Control ◽  
First Time

AbstractFor the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

scholarly journals Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure

2018 ◽  
Vol 8 (1) ◽  
pp. 421
Author(s):  
Amine Mohammed Taberkit ◽  
Ahlam Guen-Bouazza ◽  
Benyounes Bouazza
Keyword(s):  
Modeling And Simulation ◽  
Threshold Voltage ◽  
Carrier Mobility ◽  
Strained Silicon ◽  
Simulation Tool ◽  
Two Dimensional ◽  
Drive Current ◽  
Dual Channel ◽  
Simulation Results ◽  
Dimensional Simulation

The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.

9 kV 4H-SiC IGBTs with 88 mΩ·cm2 of R diff, on

2007 ◽  
Vol 556-557 ◽  
pp. 771-774 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Charlotte Jonas ◽  
Bradley Heath ◽  
Mrinal K. Das ◽  
Sei Hyung Ryu ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
High Power ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
Gate Bias ◽  
Channel Mobility ◽  
Fast Switching ◽  
Blocking Voltage ◽  
First Time

SiC IGBTs are suitable for high power, high temperature applications. For the first time, the design and fabrication of 9 kV planar p-IGBTs on 4H-SiC are reported in this paper. A differential on-resistance of ~ 88 m(cm2 at a gate bias of –20 V is achieved at 25°C, and decreases to ~24.8 m(cm2 at 200°C. The device exhibits a blocking voltage of 9 kV with a leakage current density of 0.1 mA/cm2. The hole channel mobility is 6.5 cm2/V-s at room temperature with a threshold voltage of –6.5 V resulting in enhanced conduction capability. Inductive switching tests have shown that IGBTs feature fast switching capability at both room and elevated temperatures.

Performance of Surface Carrier Mobility for Nano-Node Strained (110) MOSFETs with Temperature Effect

2011 ◽  
Vol 291-294 ◽  
pp. 3131-3134
Author(s):  
Mu Chun Wang ◽  
Hsin Chia Yang ◽  
Wen Shiang Liao
Keyword(s):  
Mass Production ◽  
Carrier Mobility ◽  
Room Temperature ◽  
Phonon Scattering ◽  
Short Channel ◽  
Channel Mobility ◽  
Temperature Impact ◽  
Control Devices ◽  
And Control ◽  
Long Channel

Considering the increase of the driving current for nano-node MOSFET devices, source/drain (S/D) site etched and refilled with SiGe material is a promising process to promote the channel mobility due to the tensile or compressive effect. Using SiGe-S/D process comparing the performance with Si-S/D and control devices on (110) wafer to probe the nano-scale mass-production possibility is a good integration. Besides the discussion in the room temperature, the device characteristics with temperature dependence are more impressive. Through analysis for the cumulated data, the temperature impact in the performance of long channel MOSFETs is higher than that in the short channel ones. The phenomena can be attributed to the tensile or compressive effect to n- or p-MOSFETs with phonon scattering disturbance.

An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

2013 ◽  
Vol 60 ◽  
pp. 580-595 ◽  
Author(s):  
G.K. Saramekala ◽  
Abirmoya Santra ◽  
Sarvesh Dubey ◽  
Satyabrata Jit ◽  
Pramod Kumar Tiwari
Keyword(s):  
Threshold Voltage ◽  
Metal Gate ◽  
Short Channel ◽  
Soi Mosfet ◽  
Dual Metal ◽  
Threshold Voltage Model

Novel Gate Oxide Process for Realization of High Threshold Voltage in 4H-SiC MOSFET

2014 ◽  
Vol 778-780 ◽  
pp. 985-988 ◽  
Author(s):  
Masayuki Furuhashi ◽  
Toshikazu Tanioka ◽  
Masayuki Imaizumi ◽  
Naruhisa Miura ◽  
Satoshi Yamakawa
Keyword(s):  
Threshold Voltage ◽  
Carrier Mobility ◽  
Positive Charge ◽  
Deep Level ◽  
Gate Oxide ◽  
High Threshold ◽  
Interface Trap Density ◽  
Wet Oxidation ◽  
Channel Mobility ◽  
Effective Carrier

We found that threshold voltage (Vth) of a 4H-SiC MOSFET increases drastically by performing low temperature wet oxidation after nitridation in a gate oxide process. The increment of Vth depends on the wet oxidation conditions. Wet oxidation increases the interface trap density (Dit) at deep level of SiC bandgap and decreases positive charge density inside the gate oxide layer. The amount change of the interface traps and the positive charges in the gate oxide makes Vth higher without a decrease in the channel mobility. We improved the trade-off between Vth and effective carrier mobility (μeff) in the MOSFET channel, and realized a low specific on-resistance (Ron,sp) SiC-MOSFET with Vth over 5 V by using the newly developed process.

Design of Triple Gate for Sub threshold Low Power applications

2017 ◽  
Vol 67 (2) ◽  
pp. 169
Author(s):  
Flavia Princess Nesamani ◽  
Geetanjali Raveendran ◽  
V.Lakshmi Prabha
Keyword(s):  
Titanium Nitride ◽  
Threshold Voltage ◽  
Double Gate ◽  
Subthreshold Slope ◽  
Metal Gate ◽  
Short Channel ◽  
Gate Electrodes ◽  
Time Fall ◽  
Corner Effects ◽  
Novel Design

<p>A novel design of triple gate MOSFET structure with metal gate and an underlap channel is proposed to minimise the short channel and corner effects. The gate metal used is titanium nitride as well as source and drain is diffused with titanium nitride so as to increase the drive capability of the device. To obtain subthreshold threshold voltage operation of the device, the gates are kept symmetric and the gate electrodes corner segments are rounded off to minimise leakage. The device shows significant improvement over conventional double gate FinFET and triple gate device without gate corner round off device in terms of Ion, Ioff ratio, DIBL, subthreshold slope, rise time, fall time.</p>

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Sign in / Sign up

Export Citation Format

Share Document