Modeling the effects of applied stress and wafer orientation in silicon devices: from long channel mobility physics to short channel performance

2009 ◽  
Vol 8 (2) ◽  
pp. 110-123 ◽  
Author(s):  
R. Kotlyar ◽  
M. D. Giles ◽  
S. Cea ◽  
T. D. Linton ◽  
L. Shifren ◽  
...  
Keyword(s):  
Applied Stress ◽  
Short Channel ◽  
Channel Mobility ◽  
Silicon Devices ◽  
Channel Performance ◽  
Wafer Orientation ◽  
Long Channel

Performance of Surface Carrier Mobility for Nano-Node Strained (110) MOSFETs with Temperature Effect

2011 ◽  
Vol 291-294 ◽  
pp. 3131-3134
Author(s):  
Mu Chun Wang ◽  
Hsin Chia Yang ◽  
Wen Shiang Liao
Keyword(s):  
Mass Production ◽  
Carrier Mobility ◽  
Room Temperature ◽  
Phonon Scattering ◽  
Short Channel ◽  
Channel Mobility ◽  
Temperature Impact ◽  
Control Devices ◽  
And Control ◽  
Long Channel

Considering the increase of the driving current for nano-node MOSFET devices, source/drain (S/D) site etched and refilled with SiGe material is a promising process to promote the channel mobility due to the tensile or compressive effect. Using SiGe-S/D process comparing the performance with Si-S/D and control devices on (110) wafer to probe the nano-scale mass-production possibility is a good integration. Besides the discussion in the room temperature, the device characteristics with temperature dependence are more impressive. Through analysis for the cumulated data, the temperature impact in the performance of long channel MOSFETs is higher than that in the short channel ones. The phenomena can be attributed to the tensile or compressive effect to n- or p-MOSFETs with phonon scattering disturbance.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach

2019 ◽  
Vol 38 (2) ◽  
pp. 815-828
Author(s):  
Ajay Kumar Singh
Keyword(s):  
Poisson’S Equation ◽  
Analytical Models ◽  
Double Gate ◽  
Poisson's Equation ◽  
Short Channel ◽  
Content Type ◽  
Dg Mosfet ◽  
Channel Potential ◽  
Work Functions ◽  
Long Channel

Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.

Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

2002 ◽  
Vol 49 (11) ◽  
pp. 1962-1968 ◽  
Author(s):  
Xiangdong Chen ◽  
Q.C. Ouyang ◽  
Geng Wang ◽  
S.K. Banerjee
Keyword(s):  
Short Channel ◽  
Hot Carrier ◽  
Channel Performance

scholarly journals A Parametric Study of the Effects of Critical Design Parameters on the Performance of Nanoscale Silicon Devices

Nanomaterials ◽  
2020 ◽  
Vol 10 (10) ◽  
pp. 1987
Author(s):  
Faraz Kaiser Malik ◽  
Tariq Talha ◽  
Faisal Ahmed
Keyword(s):  
Heat Generation ◽  
Initial Temperature ◽  
Scattering Length ◽  
Monte Carlo Model ◽  
Generation Rate ◽  
Design Parameters ◽  
Heat Generation Rate ◽  
Short Channel ◽  
Critical Design ◽  
Silicon Devices

The current electronics industry has used the aggressive miniaturization of solid-state devices to meet future technological demands. The downscaling of characteristic device dimensions into the sub-10 nm regime causes them to fall below the electron–phonon scattering length, thereby resulting in a transition from quasi-ballistic to ballistic carrier transport. In this study, a well-established Monte Carlo model is employed to systematically investigate the effects of various parameters such as applied voltage, channel length, electrode lengths, electrode doping and initial temperature on the performance of nanoscale silicon devices. Interestingly, from the obtained results, the short channel devices are found to exhibit smaller heat generation, with a 2 nm channel device having roughly two-thirds the heat generation rate observed in an 8 nm channel device, which is attributed to reduced carrier scattering in the ballistic transport regime. Furthermore, the drain contacts of the devices are identified as critical design areas to ensure safe and efficient performance. The heat generation rate is observed to increase linearly with an increase in the applied electric field strength but does not change significantly with an increase in the initial temperature, despite a marked reduction in the electric current flowing through the device.

Study on Micropump Using Boiling Bubbles

2008 ◽  
Vol 130 (2) ◽  
Author(s):  
Yasuo Koizumi ◽  
Hiroyasu Ohtake
Keyword(s):  
Cross Section ◽  
Flow Rate ◽  
Equation Of Motion ◽  
Flow Channel ◽  
Stationary Condition ◽  
Short Channel ◽  
Short Side ◽  
Liquid Plug ◽  
Average Flow Velocity ◽  
Long Channel

A micropump was developed using boiling and condensation in a microchannel. The length and hydraulic diameter of the semi-half-circle cross-section microchannel having two open tanks at both ends were 26mm and 0.465mm, respectively. A 0.5×0.5mm2 electrically heated patch was located at the offset location from the center between both ends of the microchannel, at a distance of 8.5mm from one end and at a distance of 17mm from the other end. The microchannel and the two open tanks were filled with distilled water. The heating patch was heated periodically to cause cyclic formation of a boiling bubble and its condensation. By this procedure, flow from the short side (8.5mm side) to the long side was created. The flow rate increased as the heating rate was increased. The obtained maximum average flow velocity and flow rate were 10.4mm∕s and 2.16mm3∕s, respectively. The velocity of an interface between the bubble and the liquid plug during the condensing period was much faster than that during the boiling period. During the condensing period, the velocity of the interface at the short channel side (8.5mm side) was faster than that at the long channel side (17mm side). The equation of motion of liquid in the flow channel was solved in order to calculate the travel of liquid in the flow channel. The predicted velocities agreed well with the experimental results. The velocity differences between the short side and the long side, as well as those between the boiling period and the condensing period, were expressed well by the calculation. Liquid began to move from the stationary condition during both the boiling and the condensing periods. The liquid in the inlet side (short side) moved faster than that in the outlet side (long side) during the condensing period because the inertia in the short side was lower than that in the long side. Since the condensation was much faster than boiling, this effect was more prominent during the condensing period. By iterating these procedures, the net flow from the short side to the long side was created.

Ac and Dc Characterization and Spice Modeling of Short Channel Polysilicon Tfts

1996 ◽  
Vol 424 ◽  
Author(s):  
M. D. Jacunski ◽  
M. S. Shur ◽  
T. Ytterdal ◽  
A. A. Owusu ◽  
M. Hack
Keyword(s):  
Frequency Dispersion ◽  
Channel Length ◽  
Short Channel ◽  
Spice Model ◽  
Dc Characteristics ◽  
Physically Based ◽  
In Series ◽  
Drain Bias ◽  
Long Channel ◽  
Good Agreement

AbstractWe present an analytical SPICE model for the AC and DC characteristics of n and p channel polysilicon TFTs which scales fully with channel length and width in all regimes of operation (leakage, subthreshold, above threshold, and kink) and accounts for the frequency dispersion of the capacitance. Once physically based parameters have been extracted from long channel TFTs, which include the gate length and drain bias dependencies of the device parameters, our model accurately reproduces short channel device characteristics. The AC model includes the input channel resistance in series with the gate oxide capacitance. As a result, our model is able to fit the frequency dispersion of the device capacitances. The model has been implemented in the AIM-Spice simulator and good agreement is observed between measured and modeled results for gate lengths down to 4 gim.

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