A Capacitor-Free CMOS Low-Noise, Low-Dropout Regulator for Capacitive Micro-Machined Accelerometer Application

2011 ◽  
Vol 483 ◽  
pp. 97-102
Author(s):  
Bing Jun Lv ◽  
Peng Fei Wang ◽  
Xiao Wei Liu ◽  
Liang Yin ◽  
Na Xu
Keyword(s):  
Low Frequency ◽  
Low Noise ◽  
Point Of View ◽  
Cmos Process ◽  
Theoretical Point ◽  
Load Current ◽  
Error Amplifier ◽  
Output Noise ◽  
Ldo Regulator ◽  
Micro Accelerometer

A capacitor-free CMOS low-noise, low-dropout (LDO) regulator for Micro-accelerometer is presented. Noise performance of the regulator is studied from a theoretical point of view and a chopper stabilized error amplifier is designed to minimize output noise. By adopting pole-zero frequency compensation technique, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability when the load current is switched by micro-accelerometer. The proposed LDO is designed and fabricated on a 2μm CMOS process. From the simulation results, it shows that the line regulation is 3.5mV/V and the load regulation is 0.33mV/mA when the load current changes from 0 to 30 mA. The experimental results show that the output noise of the regulator is less than 180nV/sqrt(Hz) at low frequency

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

2017 ◽  
Vol 26 (12) ◽  
pp. 1750197 ◽  
Author(s):  
Fatemeh Abdi ◽  
Mahnaz Janipoor Deylamani ◽  
Parviz Amiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Load Current ◽  
Rate Enhancement ◽  
Error Amplifier ◽  
Response Enhancement

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18[Formula: see text][Formula: see text]m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5–3.3[Formula: see text]V, the output voltage after 25[Formula: see text][Formula: see text]s with load current of 100[Formula: see text]mA, is determined with ripple less than 1.8[Formula: see text]mV. In sudden changes, the load current at the range 0–100[Formula: see text]mA, and output voltages after a maximum 15.5[Formula: see text][Formula: see text]s with an input voltage of 3.3[Formula: see text]V have the highest ripple in output voltage of 4[Formula: see text]mV.

A High-Performance Interface ASIC for Quartz Rate Sensor

2011 ◽  
Vol 483 ◽  
pp. 471-474
Author(s):  
Wei Ping Chen ◽  
Qing Yi Wang ◽  
Liang Yin ◽  
Zhi Ping Zhou
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Performance ◽  
Low Noise ◽  
Stable Operation ◽  
Cmos Process ◽  
Test Results ◽  
Bias Stability ◽  
Output Noise ◽  
Rate Sensor

In this work, an ASIC interface for quartz rate sensor (QRS) is introduced. Based on 0.6μm 18V N-well CMOS process, it is the first to be realized in the domestic. This chip has a minimized size of 5×4.4mm2. Compared with traditional interface constructed by separate devices, such interface implemented with integrated circuits is advantageous in size and power consumption. This satisfies the requirements of miniature and low power consumption in space industry and military domain. The test results show that this interface features low noise, high linearity, and stable operation. Integrated with the sensor, the entire system presents high performance in short term bias stability, nonlinearity, output noise, bias variation over temperature, and power consumption.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

Study of a closed-loop high-precision front-end circuit for tunneling magneto-resistance sensors

2019 ◽  
Vol 33 (08) ◽  
pp. 1950085 ◽  
Author(s):  
Xiangyu Li ◽  
Jianping Hu ◽  
Xiaowei Liu
Keyword(s):  
High Precision ◽  
Closed Loop ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Corner Frequency ◽  
Cmos Process ◽  
Interface Circuit ◽  
Front End ◽  
Magneto Resistance

A closed-loop high-precision front-end interface circuit in a standard 0.35 [Formula: see text]m CMOS technology for a tunneling magneto-resistance (TMR) sensor is presented in this paper. In consideration of processing a low frequency and weak geomagnetic signal, a low-noise front-end detection circuit is proposed with chopper technique to eliminate the 1/f noise and offset of operational amplifier. A novel ripple suppression loop is proposed for eliminating the ripple in a tunneling magneto-resistance sensor interface circuit. Even harmonics is eliminated by fully differential structure. The interface is fabricated in a standard 0.35 [Formula: see text]m CMOS process and the active circuit area is about [Formula: see text]. The interface chip consumes 7 mW at a 5 V supply and the 1/f noise corner frequency is lower than 1 Hz. The interface circuit of TMR sensors can achieve a better noise level of [Formula: see text]. The ripple can be suppressed to less than 10 [Formula: see text]V by ripple suppression loop.

scholarly journals Low-Noise Chopper-Stabilized Multi-Path Operational Amplifier with Nested Miller Compensation for High-Precision Sensors

2019 ◽  
Vol 10 (1) ◽  
pp. 281 ◽  
Author(s):  
Jaesung Kim ◽  
Hyungseup Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
High Precision ◽  
Operational Amplifier ◽  
High Frequency ◽  
Flicker Noise ◽  
Low Frequency ◽  
Low Noise ◽  
Cmos Process ◽  
Miller Compensation ◽  
Chopper Stabilization ◽  
Nested Miller Compensation

This paper presents a low-noise multi-path operational amplifier for high-precision sensors. A chopper stabilization technique is applied to the amplifier to remove offset and flicker noise. A ripple reduction loop (RRL) is designed to remove the ripple generated in the process of up-modulating the flicker noise and offset. To cancel the notch in the overall transfer function due to the RRL operation, a multi-path architecture using both a low-frequency path (LFP) and high-frequency path (HFP) is implemented. The low frequency path amplifier is implemented using the chopper technique and the RRL. In the high-frequency path amplifier, a class-AB output stage is implemented to improve the power efficiency. The transfer functions of the LFP and HFP induce a first-order frequency response in the system through nested Miller compensation. The low-noise multi-path amplifier was fabricated using a 0.18 µm 1P6M complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the proposed low-noise operational amplifier is 0.174 mW with a 1.8 V supply and an active area of 1.18 mm2. The proposed low-noise amplifier has a unit gain bandwidth (UGBW) of 3.16 MHz, an input referred noise of 11.8 nV/√Hz, and a noise efficiency factor (NEF) of 4.46.

A High Uniformity Readout Integrated Circuit for Infrared Focal Plane Array Applications

2014 ◽  
Vol 602-605 ◽  
pp. 2632-2636
Author(s):  
Tong Zhou ◽  
Tao Dong ◽  
Yan Su ◽  
Yong He
Keyword(s):  
Integrated Circuit ◽  
Focal Plane ◽  
Infrared Image ◽  
Low Frequency ◽  
Low Noise ◽  
Focal Plane Arrays ◽  
Cmos Process ◽  
Readout Integrated Circuit ◽  
Practical Applications ◽  
High Uniformity

Infrared focal plane arrays (IRFPA) suffer from inherent low frequency and fixed patter noise (FPN). To achieve high quality infrared image by mitigating the FPN of IRFPAs, a novel low-noise and high uniformity readout integrated circuit (ROIC) has been proposed. A correlated double sampling (CDS) with single capacitor method has been adopted in the ROIC design which can effectively reduce the FPN, KTC and 1/f noise. A 4×4 experimental readout chip has been designed and fabricated using the SMIC 0.18 μm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental results. The test results show that the proposed ROIC has a good performance in practical applications.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Proposal and design methodology of switching mode low dropout regulator for Bio-medical applications

2019 ◽  
Vol 9 (6) ◽  
pp. 5046
Author(s):  
Kenya Kondo ◽  
Hiroki Tamura ◽  
Koichi Tanno
Keyword(s):  
Low Frequency ◽  
Design Procedure ◽  
Logic Gates ◽  
Maximum Load ◽  
Cmos Process ◽  
Light Load ◽  
Analog Front End ◽  
Low Dropout Regulator ◽  
Switching Mode ◽  
Ldo Regulator

<p>The switching operation based low dropout (LDO) regulator utilizing on-off control is pre-sented. It consists of simple circuit elements which are comparator, some logic gates, switched capacitor and feedback circuit. In this study, we target the application to the power supply circuit for the analog front end (AFE) of bio-medical system (such as daily-used bio-monitoring devices) whose required maximum load current is 50 A. In this paper, the design procedure of the proposed LDO has been clarified and actual circuit design using the procedure has been done. The proposed LDO has been evaluated by SPICE simulation using 1P 2M 0.6 m CMOS process device parameters. From simulation results, we could confirm that the low quiescent current of 1 A with the output ripple of 5 mVpp. The circuit area is 0.0173 mm2 in spite of using 0.6 m design rules. The proposed circuit is suitable for adopting to the light load and low frequency applications.</p>

scholarly journals A LOW-NOISE LOW-POWER SECOND-ORDER COMPENSATED CMOS BANDGAP REFERENCE

2016 ◽  
Vol 9 (1) ◽  
Author(s):  
Sigit Yuwono ◽  
Arie Van Staveren
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Second Order ◽  
Current Gain ◽  
Voltage Source ◽  
Cmos Process ◽  
Temperature Dependency ◽  
Bandgap Reference ◽  
Current Consumption ◽  
Output Noise

The design of a low-noise and low-power second-order bandgap reference voltage source using a linear combination of two base-emitter voltages with only one scaling factor is treated. The design takes into account the temperature dependency of the resistors and the finite current gain of BJT�s. The circuit is integrated in a CMOS process. The output voltage is approximately 140 mV with an average temperature dependency of 22.5 ppm/K in the range of 0�C to 120�C. Its equivalent output noise voltage is 57.6nV/vHz. The total current consumption is about 115 �A from a 2V voltage-supply.Keywords: bandgap reference, negative feedback, systematic design.

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