scholarly journals LOW POWER ASIC IMPLEMENTATION OF A 256 BIT KEY AES CRYPTO-PROCESSOR AT 45NM TECHNOLOGY

2014 ◽  
pp. 177-181
Author(s):  
ASHWIN R ◽  
SAROJA S BHUSARE
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Power Reduction ◽  
Security Level ◽  
Power Gating ◽  
Power Devices ◽  
Verilog Hdl ◽  
Cell Library ◽  
The Past ◽  
Important Design

Advanced Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. Low power devices have gained extreme importance in market today. Power dissipation is one of the most important design constraints to be handled well. A key to successful power management is automatic power reduction. This enables designers to meet their power budgets without adversely affecting their productivity or time to market. In this paper power gating techniques applied on AES crypto-processor is depicted. The goal of power gating is to minimize leakage power by temporarily cutting power off to selective blocks that are not required in the current operation. This AES design was implemented using Verilog HDL and synthesized with Synopsys DC Compiler using Nangate 45 nm open cell library, physical design implementation and power gating was performed using SOC Encounter and achieved a power reduction up to 40%.

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 108-124 ◽  
Author(s):  
Mahshid Mojtabavi Naeini ◽  
Sreedharan Baskara Dass ◽  
Chia Yee Ooi ◽  
Tomokazu Yoneda ◽  
Michiko Inoue
Keyword(s):  
Low Power ◽  
Power Reduction ◽  
Power Gating ◽  
Scan Test

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals An Innovative Low Power Reversible ALU for Quantum Processor using QCA

2019 ◽  
Vol 8 (12) ◽  
pp. 2903-2908
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Reversible Logic ◽  
Heat Energy ◽  
Delay Analysis ◽  
Verilog Hdl ◽  
Basic Part ◽  
Quantum Processor ◽  
Cadence Tool ◽  
Reversible Alu

Landauer stated that “For irreversible computation each loss in information leads to loss of kTln2 joules of heat energy”. This has led to considerable interest in reversible logic. We know that ALU is the most basic part in any processor. Processor quality is determined based on its speed of operation. But, as the size of a processor decreases we face problems like power dissipation and greater delays. So, this paper presents an ALU implemented using reversible logic. This design is a simple way to reduce power dissipation and delay to a certain extent. Verilog HDL programming has been used to make this design. We have used XILINX and CADENCE tool to simulate this model and obtain power and delay analysis.

Design Methodology for Multipliers with Active Leakage and Dynamic Power Reduction

2012 ◽  
Vol 182-183 ◽  
pp. 1440-1445
Author(s):  
Xi Tian ◽  
Fei Qiao ◽  
Zai Wang Dong ◽  
Yu Jun Liu ◽  
Yu Ting Zhao
Keyword(s):  
Input Signal ◽  
Power Dissipation ◽  
Design Methodology ◽  
Dynamic Range ◽  
Power Reduction ◽  
Total Power ◽  
Power Gating ◽  
Dynamic Power ◽  
On Chip ◽  
Novel Design

A novel design methodology for multipliers to reducing both active leakage and dynamic power using dynamic power gating is presented, where sleep transistors are inserted between the real and virtual ground rails of various parts of the multiplier which could be selectively turned on/off. On-chip sleep signals are generated from one input signal of the multiplier which has larger dynamic range. By detecting the magnitude of the input signal, the idle parts of the multiplier are identified and the power gating schemes are dynamically applied even when the multiplier is performing useful computation. Simulations show that the total power dissipation of the proposed multiplier could be reduced up to 39.3% in a typical DSP application.

scholarly journals Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

2021 ◽  
Vol 15 ◽  
Author(s):  
Pavan Kumar Chundi ◽  
Dewei Wang ◽  
Sung Justin Kim ◽  
Minhao Yang ◽  
Joao Pedro Cerqueira ◽  
...  
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
State Of The Art ◽  
Spiking Neural Network ◽  
Power Gating ◽  
Ultra Low Power ◽  
Fine Grained ◽  
Input Activity

This paper presents a novel spiking neural network (SNN) classifier architecture for enabling always-on artificial intelligent (AI) functions, such as keyword spotting (KWS) and visual wake-up, in ultra-low-power internet-of-things (IoT) devices. Such always-on hardware tends to dominate the power efficiency of an IoT device and therefore it is paramount to minimize its power dissipation. A key observation is that the input signal to always-on hardware is typically sparse in time. This is a great opportunity that a SNN classifier can leverage because the switching activity and the power consumption of SNN hardware can scale with spike rate. To leverage this scalability, the proposed SNN classifier architecture employs event-driven architecture, especially fine-grained clock generation and gating and fine-grained power gating, to obtain very low static power dissipation. The prototype is fabricated in 65 nm CMOS and occupies an area of 1.99 mm2. At 0.52 V supply voltage, it consumes 75 nW at no input activity and less than 300 nW at 100% input activity. It still maintains competitive inference accuracy for KWS and other always-on classification workloads. The prototype achieved a power consumption reduction of over three orders of magnitude compared to the state-of-the-art for SNN hardware and of about 2.3X compared to the state-of-the-art KWS hardware.

scholarly journals Low-Power RTL Code Generation for Advanced CNN Algorithms toward Object Detection in Autonomous Vehicles

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 478
Author(s):  
Youngbae Kim ◽  
Heekyung Kim ◽  
Nandakishor Yadav ◽  
Shuai Li ◽  
Kyuwon Ken Choi
Keyword(s):  
Low Power ◽  
Object Detection ◽  
Power Dissipation ◽  
Detection System ◽  
Data Access ◽  
Power Reduction ◽  
Design Flow ◽  
Ultra Low Power ◽  
Dynamic Power ◽  
Asic Design

In the implementation process of a convolution neural network (CNN)-based object detection system, the primary issues are power dissipation and limited throughput. Even though we utilize ultra-low power dissipation devices, the dynamic power dissipation issue will be difficult to resolve. During the operation of the CNN algorithm, there are several factors such as the heating problem generated from the massive computational complexity, the bottleneck generated in data transformation and by the limited bandwidth, and the power dissipation generated from redundant data access. This article proposes the low-power techniques, applies them to the CNN accelerator on the FPGA and ASIC design flow, and evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45 nm technology for ASIC, respectively. Our proposed low-power techniques are applied at the register-transfer-level (RT-level), targeting FPGA and ASIC. In this article, we achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low-power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the CNN-based object detection system.

A Radix-16 Booth Multiplier Based on Recoding Adder with Ultra High Power Efficiency and Reduced Complexity for Neuroimaging

2020 ◽  
Vol 10 (4) ◽  
pp. 814-821
Author(s):  
J. Sureshbabu ◽  
G. Saravanakumar
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Power Dissipation ◽  
Power Efficiency ◽  
High Speed ◽  
Average Power ◽  
Vlsi Design ◽  
Propagation Time ◽  
Power Gating ◽  
Booth Multiplier

In the current medical developments the neuro imaging plays a vital role in the study of a human brain related disorders. The accuracy of the brain study is mainly dependent on the images created from the scanners at a rapid speed. In achieving this we need a high speed and low power consuming scanners. The current scenario in VLSI design, the scanners highly rely on a high speed Digital Signal Processor (DSP), which generally depends on the speed of a multiplier. Multipliers are considered as a more complex component when compared with adders. The current techniques provide greater access to high-speed multipliers which are designed with less area that consume low power. The major constraints to be considered for an efficient multiplier design are propagation time delay and power dissipation, especially during the ideal time. An approximate recoding adder is proposed to reduce the existing booth multiplier's immensity. It increases the accuracy and reduces complexity through this technique; however, it has an issue with Power Delay Product (PDP) and power dissipation. To solve this problem, the proposed system is designed with a power gating based 16 × 16 bit Booth multiplier based on approximate recoding adder. It decreases the power dissipation and minimizes the length and width of the partial products for speeding up the multiplication process. The results obtained from the simulation show that the designed power gating based Radix multiplier circuits achieves better PDP, average power and area. The achieved results are compared with a Radix based multiplier, power gating CLA based multiplier and CLA based multiplier.

scholarly journals LOW POWER VLSI TECHNIQUES FOR PORTABLE DEVICES

2020 ◽  
Vol 5 (2) ◽  
pp. 223-232
Author(s):  
Sandeep Singh ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Low Power Design ◽  
Vital Role ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Design Strategies ◽  
Power Devices ◽  
Dynamic Power

In the present day scenario, designing a circuit with low power has become very important and challenging task. The designing of any processor for portable devices demands low power. This can be achieved by incorporating low power design strategies and rules at various stages of design. To increase the performance of portable devices, the power backup should be taken in consideration, which is extremely desirable from the users prospective. As we approaches towards the sub-micron technology the requirement of low power devices increases significantly. But at the same time leakage current and dynamic power dissipation play a vital role to diminish the performance of portable devices. This paper presents techniques to reduce the power dissipation and various methodologies to increase the speed of device. That is very beneficial for designing of future VLSI circuits.

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