The impact of total ionizing dose on RF performance of 130 nm PD SOI I/O nMOSFETs

2021 ◽  
Vol 116 ◽  
pp. 114001
Author(s):  
Tiantian Xie ◽  
Hao Ge ◽  
Yinghuan Lv ◽  
Jing Chen
Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 3121
Author(s):  
Monica La Mura ◽  
Patrizia Lamberti ◽  
Vincenzo Tucci

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.


2008 ◽  
Vol 55 (6) ◽  
pp. 3280-3287 ◽  
Author(s):  
Xiaoyin Yao ◽  
Nathan Hindman ◽  
Lawrence T. Clark ◽  
Keith E. Holbert ◽  
David R. Alexander ◽  
...  

2002 ◽  
Vol 23 (6) ◽  
pp. 309-311
Author(s):  
L. Pantisano ◽  
K.P. Cheung ◽  
P.J. Roussel ◽  
A. Paccagnella

2021 ◽  
Author(s):  
Sarita Misra ◽  
Sudhansu Mohan Biswal ◽  
Biswajit Baral ◽  
Sanjit Kumar Swain ◽  
Sudhansu Kumar Pati

Abstract This paper explores the potential advantage of surrounded gate junctionless graded channel (SJLGC) MOSFET in the view of its Analog, RF performances using ATLAS TCAD device simulator. The impact of graded channel in the lateral direction on the potential, electric field, and velocity of carriers, energy band along the channel is investigated systematically. The present work mainly emphasises on the superior performance of SJLGC MOSFET by showing higher drain current (ID) , transconductance (gm) ,cut off frequency (fT) , maximum frequency of oscillation (fmax) , critical frequency (fK) .The drain current is improved by 10.03 % in SJLGC MOSFET due to the impact of grading the channel. There is an improvement in fT, fmax, fK by 45%, 29% and 18% respectively in SJLGC MOSFET showing better RF Performance. The dominance of the SJLGC MOSFET over SJL MOSFET is further elucidated by showing 74% improvement in intrinsic voltage gain (gm / gds) indicating its better applications in sub threshold region. But the transconductance generation factor of SJLGC MOSFET is less than SJL MOSFET in the subthreshold region. The intrinsic gate delay (ζD) of SJLGC MOSFET is less in comparison to SJL MOSFET due to the impact of lower gate to gate capacitance (CGG) suggesting better digital switching applications. The simulation results reveal that SJLGC MOSFET can be a competitive contender for the coming generation of RF circuits covering a broad range of operating frequencies in RF spectrum.


Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 2133 ◽  
Author(s):  
Anna Persano ◽  
Fabio Quaranta ◽  
Antonietta Taurino ◽  
Pietro Aleardo Siciliano ◽  
Jacopo Iannacci

In this work, SiNx/a-Si/SiNx caps on conductive coplanar waveguides (CPWs) are proposed for thin film encapsulation of radio-frequency microelectromechanical systems (RF MEMS), in view of the application of these devices in fifth generation (5G) and modern telecommunication systems. Simplification and cost reduction of the fabrication process were obtained, using two etching processes in the same barrel chamber to create a matrix of holes through the capping layer and to remove the sacrificial layer under the cap. Encapsulating layers with etch holes of different size and density were fabricated to evaluate the removal of the sacrificial layer as a function of the percentage of the cap perforated area. Barrel etching process parameters also varied. Finally, a full three-dimensional finite element method-based simulation model was developed to predict the impact of fabricated thin film encapsulating caps on RF performance of CPWs.


2020 ◽  
Vol 34 (27) ◽  
pp. 2050242
Author(s):  
Shradhya Singh ◽  
Sangeeta Singh ◽  
Alok Naugarhiya

This paper addresses the effect of temperature variation on the performance of a novel device structure Si-doped Hf[Formula: see text] negative capacitance junctionless tunnel field effect transistor (Si:Hf[Formula: see text] NC-JLTFET). Here, Si:Hf[Formula: see text] ferroelectric material is deployed as gate stack along with high-K gate dielectric Hf[Formula: see text]. Si:Hf[Formula: see text] ferroelectric material generates NC effect during the device operation. This phenomenon is an effective technique for intrinsic voltage amplification, reduction in power supply, as well as minimization of power dissipation. The proposed device structure has two variants, symmetric and asymmetric with respect to the oxide thickness between electrode and Si body at both drain and source sides. As band-to-band tunneling in TFET is temperature dependent, it is very crucial to analyze the impact of temperature variation on the device performance. This work is mainly focused on investigating the device dc performance parameters, analog/RF performance parameters and linearity performance parameters by observing the impact of temperature variation. The device characteristics reveal that for dc and RF performance parameters, asymmetric structure shows better result. Highest [Formula: see text] ratio and minimum SS are reported as [Formula: see text] and 20.038 mV/dec, respectively, at 300K for asymmetric structure. At elevated temperatures higher cutoff frequency and reduced intrinsic delay project the device as a strong candidate for ultra low-power and high switching speed applications. Further, the reported device shows better linearity performance at higher temperatures.


2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000064-000071
Author(s):  
Thomas Bartnitzek ◽  
Tatyana Purtova ◽  
Christian Rusch ◽  
Slawomir Kaminski ◽  
Till Feger

RF packaging is one of the most challenging topics in LTCC technology. Today LTCC is particularly capable for advanced packages and systems-in-package because of its electrical, functional, thermomechanical properties as well as its excellent long-term stability and reliability. LTCC combines the potential for miniaturization, low loss handling of high frequencies up to 110 GHz and offers the opportunity to integrate additional features. Therefore it has to go through various manufacturing steps and several refirings without any performance degradation or loss of dimensional accuracy. This paper discusses the impact of thermal post processing on RF characteristics and geometrical properties of LTCC. Ceramic substrates with radar front ends, calibration structures and other test vehicles made of Du Pont Green Tape® 943 and 9k7 were cofired following the recommended conditions and refired several times in order to investigate and compare the influence of the postfiring. The flatness, dimensions and RF performance of the ceramics up to 110 GHz were evaluated and compared.


Author(s):  
M. Hosch ◽  
R. Behtash ◽  
J.R. Thorpe ◽  
S. Held ◽  
H. Blanck ◽  
...  
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