Prediction of thermal conductivity and phonon spectral of silicon material with pores for semiconductor device

2021 ◽  
pp. 413034
Author(s):  
Jia Chen ◽  
Xiaobing Zhang
Keyword(s):  
Thermal Conductivity ◽  
Semiconductor Device ◽  
Silicon Material

scholarly journals Analysis of Warpage Induced by Thick Copper Metal on Semiconductor Device

2021 ◽  
pp. 55-60
Author(s):  
Michele Calabretta ◽  
Alessandro Sitta ◽  
Salvatore Massimo Oliveri ◽  
Gaetano Sequenzia
Keyword(s):  
Thermal Conductivity ◽  
Semiconductor Device ◽  
Semiconductor Industry ◽  
Technological Factor ◽  
Element Model ◽  
Annealing Process ◽  
Copper Layer ◽  
Analytical Models ◽  
Linear Finite Element ◽  
State Of Art

AbstractElectrochemical deposited (ECD) thick film copper on silicon substrate is one of the most challenging technological brick for semiconductor industry representing a relevant improvement from the state of art because of its excellent electrical and thermal conductivity compared with traditional compound such as aluminum. The main technological factor that makes challenging the industrial implementation of thick copper layer is the severe wafer warpage induced by Cu annealing process, which negatively impacts the wafer manufacturability. The aim of presented work is the understanding of warpage variation during annealing process of ECD thick (~20 µm) copper layer. Warpage has been experimental characterized at different temperature by means of Phase-Shift Moiré principle, according to different annealing profiles. A linear Finite Element Model (FEM) has been developed to predict the geometrically stress-curvature relation, comparing results with analytical models.

Hydrogenation in Crystalline Silicon Materials for Photovoltaic Application

2009 ◽  
Vol 156-158 ◽  
pp. 343-349 ◽  
Author(s):  
Giso Hahn ◽  
Martin Käs ◽  
Bernhard Herzog
Keyword(s):  
Charge Carrier ◽  
Surface Passivation ◽  
Semiconductor Device ◽  
Crystalline Silicon ◽  
Device Fabrication ◽  
Silicon Material ◽  
Photovoltaic Application ◽  
Dielectric Layers ◽  
Annealing Step ◽  
Silicon Materials

In this contribution an overview of hydrogenation issues for (multi-)crystalline silicon material is given. Crystalline silicon material for photovoltaic application contains more defects than material used for other semiconductor device fabrication. Therefore passivation of bulk defects has to be performed to reach higher efficiencies and exploit the cost reduction potential of these materials. Especially minority charge carrier lifetimes of ribbon silicon can be drastically improved by hydrogenation in combination with a gettering step. Apart from bulk passivation atomic hydrogen plays an important role in surface passivation via dielectric layers. Performance of single dielectric layers or stack systems can be increased after a hydrogenation step. It is believed that hydrogen can passivate defects at the silicon/dielectric interface allowing for lower surface recombination velocities. In industrial application hydrogenation is performed via deposition of a hydrogen-rich PECVD SiNx layer followed by a belt furnace annealing step. Surface passivation for characterization of charge carrier bulk lifetime is often performed with the same technique, omitting the annealing step to avoid in-diffusion of hydrogen. It is shown that for some crystalline silicon materials even the PECVD SiNx deposition alone (without annealing step) can cause significant bulk defect passivation, which in this case causes an unwanted change of bulk lifetime.

Thermal Transport in Novel Silicon Transistors

2004 ◽  
Author(s):  
Keivan Etessam-Yazdani ◽  
Wenjun Liu ◽  
Yizhang Yang ◽  
Mehdi Asheghi
Keyword(s):  
Thermal Conductivity ◽  
Semiconductor Device ◽  
Silicon Layer ◽  
Phonon Transport ◽  
Interface Roughness ◽  
Strained Silicon ◽  
Boltzmann Transport ◽  
Strained Si ◽  
Thin Silicon ◽  
The Impact

This manuscript investigates the relevance and impact of nanoscale thermal phenomena in the state-of-the-art semiconductor device technologies such as: silicon-on-insulator (SOI), strained silicon, and tri-gate CMOS transistors. The experimental data and predictions for thin silicon layer thermal conductivity and the solutions of the Boltzmann transport equations (BTE) for phonon transport in strained-Si/Ge bi-layer configuration are used to estimate the thermal resistance of the SOI, tri-gate, and strained-silicon-on-SiGe-on-insulator (SGOI) transistors, respectively. In particular, the impact of SiGe underlayer and interface roughness on the lateral thermal conductivity of the silicon layer at room temperature is investigated. In order to avoid the complexity of the BTE for predictions of the temperature distribution, Lumped Analytical (LA) models are introduced that are simple to implement and also adequate enough to capture the sub-continuum effects. It is concluded that the SOI, SGOI and tri-gate transistors are all susceptible to self-heating for very thin silicon device layers.

Redesigns of HSOP Package for High Power Consumption Based on the Numerical Thermal Simulation Analysis

2005 ◽  
Author(s):  
John Chia ◽  
Jinfa Chen
Keyword(s):  
Thermal Conductivity ◽  
Power Consumption ◽  
Thermal Performance ◽  
Semiconductor Device ◽  
Simulation Analysis ◽  
Functional Integration ◽  
Internal Heat ◽  
Frame Design ◽  
Reliability Issue ◽  
Standard Designs

A Heat Slug Outline Package (HSOP) with different design concepts to improve its thermal performance is investigated. The thermal performance of the standard designs of TSSOP usually could not pass the requirements for greater functional integration in wireless frquency and reduction in power consumption, e.g. for a radio frequency (RF) front-end IC’s in silicon its power consumption can be increased about twice when the design frequency increases from 2.0 GHz to 3.5 GHz. The configuration of HSOP28 proposed here is redesigned based on the Thin Shrink Small Outline Package (TSSOP) that is a plastic encapsulated semiconductor device complied with a standard Surface Mount Technology (SMT). In order to accommodate a chip with the same size but double it power consumption, various types of lead frame design for HSOP packages are studies. It is therefore an object of the present study to investigate what will be the maximum thermal improvement of HSOP package compared to the corresponding same size of TSSOP package, which is also related to further reliability issue of this type of IC package, i.e. the thermal fatigue life calculation. Studies presented here are also taken into account the thermal performance of HSOP package associated with different multi-layers PCB designs and the thermal conductivity variations, where the package internal heat conduction as function of board thermal conductivity can be made.

Defects in β-SiC thin films grown on α-SiC substrates

1988 ◽  
Vol 46 ◽  
pp. 568-569
Author(s):  
Karren L. More
Keyword(s):  
Thin Films ◽  
Semiconductor Device ◽  
Lattice Mismatch ◽  
Chemical Vapor ◽  
Substrate Material ◽  
Growth Interface ◽  
Si Substrates ◽  
Thermal Expansion Coefficients ◽  
Device Applications ◽  
Expansion Coefficients

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

Applications of SIMS to electronic materials and devices

1992 ◽  
Vol 50 (2) ◽  
pp. 1682-1683
Author(s):  
S.F. Corcoran
Keyword(s):  
Depth Distribution ◽  
Secondary Ion Mass Spectrometry ◽  
Semiconductor Device ◽  
Electronic Materials ◽  
Profile Analysis ◽  
Semiconductor Industry ◽  
Small Diameter ◽  
Depth Resolution ◽  
Detection Sensitivity

Over the past decade secondary ion mass spectrometry (SIMS) has played an increasingly important role in the characterization of electronic materials and devices. The ability of SIMS to provide part per million detection sensitivity for most elements while maintaining excellent depth resolution has made this technique indispensable in the semiconductor industry. Today SIMS is used extensively in the characterization of dopant profiles, thin film analysis, and trace analysis in bulk materials. The SIMS technique also lends itself to 2-D and 3-D imaging via either the use of stigmatic ion optics or small diameter primary beams.By far the most common application of SIMS is the determination of the depth distribution of dopants (B, As, P) intentionally introduced into semiconductor materials via ion implantation or epitaxial growth. Such measurements are critical since the dopant concentration and depth distribution can seriously affect the performance of a semiconductor device. In a typical depth profile analysis, keV ion sputtering is used to remove successive layers the sample.

Structural and electronic properties of defects in semiconductors

1995 ◽  
Vol 53 ◽  
pp. 4-5
Author(s):  
J.L. Batstone
Keyword(s):  
Semiconductor Device ◽  
Chemical Vapor ◽  
Misfit Strain ◽  
Organic Chemical ◽  
Extended Defects ◽  
Transmission Electron ◽  
Semiconductor Thin Films ◽  
Wide Range ◽  
Metal Organic ◽  
Film Substrate

The development of growth techniques such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy during the last fifteen years has resulted in the growth of high quality epitaxial semiconductor thin films for the semiconductor device industry. The III-V and II-VI semiconductors exhibit a wide range of fundamental band gap energies, enabling the fabrication of sophisticated optoelectronic devices such as lasers and electroluminescent displays. However, the radiative efficiency of such devices is strongly affected by the presence of optically and electrically active defects within the epitaxial layer; thus an understanding of factors influencing the defect densities is required.Extended defects such as dislocations, twins, stacking faults and grain boundaries can occur during epitaxial growth to relieve the misfit strain that builds up. Such defects can nucleate either at surfaces or thin film/substrate interfaces and the growth and nucleation events can be determined by in situ transmission electron microscopy (TEM).

Metal Microstructures in Advanced CMOS Devices

1996 ◽  
Vol 54 ◽  
pp. 358-359
Author(s):  
L. M. Gignac ◽  
K. P. Rodbell
Keyword(s):  
Grain Boundaries ◽  
Semiconductor Device ◽  
Chemical Vapor ◽  
Microstructural Characterization ◽  
Metal Films ◽  
Thin Metal ◽  
Electrical Performance ◽  
Thin Metal Films ◽  
Chemical Vapor Deposited ◽  
Boundary Properties

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

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