scholarly journals Ferroelectric-based synapses and neurons for neuromorphic computing

2022 ◽  
Author(s):  
Erika Covi ◽  
Halid Mulaosmanovic ◽  
Benjamin Max ◽  
Stefan Slesazeck ◽  
Thomas Mikolajick
Keyword(s):  
Power Efficiency ◽  
Response Times ◽  
Internal State ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Fast Response ◽  
Oxide Semiconductor ◽  
Neuromorphic Computing ◽  
Power Efficient ◽  
Multiple Systems

Abstract The shift towards a distributed computing paradigm, where multiple systems acquire and elaborate data in real-time, leads to challenges that must be met. In particular, it is becoming increasingly essential to compute on the edge of the network, close to the sensor collecting data. The requirements of a system operating on the edge are very tight: power efficiency, low area occupation, fast response times, and on-line learning. Brain-inspired architectures such as Spiking Neural Networks (SNNs) use artificial neurons and synapses that simultaneously perform low-latency computation and internal-state storage with very low power consumption. Still, they mainly rely on standard complementary metal-oxide-semiconductor (CMOS) technologies, making SNNs unfit to meet the aforementioned constraints. Recently, emerging technologies such as memristive devices have been investigated to flank CMOS technology and overcome edge computing systems' power and memory constraints. In this review, we will focus on ferroelectric technology. Thanks to its CMOS-compatible fabrication process and extreme energy efficiency, ferroelectric devices are rapidly affirming themselves as one of the most promising technology for neuromorphic computing. Therefore, we will discuss their role in emulating neural and synaptic behaviors in an area and power-efficient way.

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

scholarly journals CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Tree Structure ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Prefix Tree ◽  
Digital Comparator ◽  
Parallel Prefix ◽  
Transmission Gates

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Deep-Submicron Single-Gate Complementary Metal Oxide Semiconductor (CMOS) Technology Using Channel Preamorphization

1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1050-1053 ◽  
Author(s):  
Masayasu Miyake ◽  
Toshio Kobayashi ◽  
Yutaka Sakakibara ◽  
Kimiyoshi Deguchi ◽  
Mitsutoshi Takahashi
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor

A 60 GHz reconfigurable active phase shifter based on a vector modulator in 65 nm CMOS technology

2016 ◽  
Vol 8 (3) ◽  
pp. 399-404 ◽  
Author(s):  
Boris Moret ◽  
Nathalie Deltimple ◽  
Eric Kerhervé ◽  
Baudouin Martineau ◽  
Didier Belot
Keyword(s):  
Phase Shift ◽  
Phase Shifter ◽  
Complementary Metal Oxide Semiconductor ◽  
Active Phase ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Semiconductor Technology ◽  
Vector Modulator ◽  
Active Phase Shifter

This paper presents a 60 GHz reconfigurable active phase shifter based on a vector modulator implemented in 65 nm complementary metal–oxide–semiconductor technology. This circuit is based on the recombination of two differential paths in quadrature. The proposed vector modulator allows us to generate a phase shift between 0° and 360°. The voltage gain varies between −13 and −9 dB in function of the phase shift generated with a static consumption between 26 and 63 mW depending on its configuration.

scholarly journals A New Approach to the Fabrication of Memristive Neuromorphic Devices: Compositionally Graded Films

Materials ◽  
2020 ◽  
Vol 13 (17) ◽  
pp. 3680
Author(s):  
Jong-Gul Yoon
Keyword(s):  
Short Term Memory ◽  
Chemical Vapor ◽  
Complementary Metal Oxide Semiconductor ◽  
Information Storage ◽  
Oxide Semiconductor ◽  
Film Electrode ◽  
Retention Performance ◽  
Short Term ◽  
Neuromorphic Computing ◽  
Term Memory

Energy-efficient computing paradigms beyond conventional von-Neumann architecture, such as neuromorphic computing, require novel devices that enable information storage at nanoscale in an analogue way and in-memory computing. Memristive devices with long-/short-term synaptic plasticity are expected to provide a more capable neuromorphic system compared to traditional Si-based complementary metal-oxide-semiconductor circuits. Here, compositionally graded oxide films of Al-doped MgxZn1−xO (g-Al:MgZnO) are studied to fabricate a memristive device, in which the composition of the film changes continuously through the film thickness. Compositional grading in the films should give rise to asymmetry of Schottky barrier heights at the film-electrode interfaces. The g-Al:MgZnO films are grown by using aerosol-assisted chemical vapor deposition. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the films show self-rectifying memristive behaviors which are dependent on maximum applied voltage and repeated application of electrical pulses. Endurance and retention performance tests of the device show stable bipolar resistance switching (BRS) with a short-term memory effect. The short-term memory effects are ascribed to the thermally activated release of the trapped electrons near/at the g-Al:MgZnO film-electrode interface of the device. The volatile resistive switching can be used as a potential selector device in a crossbar memory array and a short-term synapse in neuromorphic computing.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

A Bio-inspired and Low-power 2D Machine Vision with Adaptive Machine Learning and Forgetting

2021 ◽  
Author(s):  
Akhil Dodda ◽  
Darsith Jayachandran ◽  
Shiva Subbulakshmi Radhakrishnan ◽  
Saptarshi Das
Keyword(s):  
Machine Vision ◽  
Energy Gap ◽  
Critical Role ◽  
Visual Stimuli ◽  
Bright Light ◽  
Complementary Metal Oxide Semiconductor ◽  
Active Role ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Large Area

Abstract Natural intelligence has many dimensions, and in animals, learning about the environment and making behavioral changes are some of its manifestations. In primates vision plays a critical role in learning. The underlying biological neural networks contain specialized neurons and synapses which not only sense and process the visual stimuli but also learns and adapts, with remarkable energy efficiency. Forgetting also plays an active role in learning. Mimicking the adaptive neurobiological mechanisms for seeing, learning, and forgetting can, therefore, accelerate the development of artificial intelligence (AI) and bridge the massive energy gap that exists between AI and biological intelligence. Here we demonstrate a bio-inspired machine vision based on large area grown monolayer 2D phototransistor array integrated with analog, non-volatile, and programmable memory gate-stack that not only enables direct learning, and unsupervised relearning from the visual stimuli but also offers learning adaptability under photopic (bright-light), scotopic (low-light), as well as noisy illumination conditions at miniscule energy expenditure. In short, our “all-in-one” hardware vision platform combines “sensing”, “computing” and “storage” not only to overcome the von Neumann bottleneck of conventional complementary metal oxide semiconductor (CMOS) technology but also to eliminate the need for peripheral circuits and sensors.

Ultrasensitive broadband photodetectors based on two-dimensional Bi2O2Te films

2021 ◽  
Author(s):  
Pin Tian ◽  
Hongbo Wu ◽  
Libin Tang ◽  
Jinzhong Xiang ◽  
Rongbin Ji ◽  
...  
Keyword(s):  
Large Scale ◽  
2D Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Photocurrent Density ◽  
Short Wave ◽  
Oxide Semiconductor ◽  
Light Illumination ◽  
Two Dimensional ◽  
Weak Light

Abstract Two-dimensional (2D) materials exhibit many unique optical and electronic properties that are highly desirable for application in optoelectronics. Here, we report the study of photodetector based on 2D Bi2O2Te grown on n-Si substrate. The 2D Bi2O2Te material was transformed from sputtered Bi2Te3 ultrathin film after rapid annealing at 400 ℃ for 10 min in air atmosphere. The photodetector was capable of detecting a broad wavelength from 210 nm to 2.4 μm with excellent responsivity of up to 3x105 and 2x104 AW-1, and detectivity of 4x1015 and 2x1014 Jones at deep ultraviolet (UV) and short-wave infrared (SWIR) under weak light illumination, respectively. The effectiveness of 2D materials in weak light detection was investigated by analysis of the photocurrent density contribution. Importantly, the facile growth process with low annealing temperature would allow direct large-scale integration of the 2D Bi2O2Te materials with complementary metal-oxide–semiconductor (CMOS) technology.

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