Three-dimensional SIW and high-performance air-filled SIW for millimeter-wave substrate integrated circuits and systems

2015 ◽  
Author(s):  
Anthony Ghiotto ◽  
Ali Doghri ◽  
Frederic Parment ◽  
Tarek Djerafi ◽  
Tan-Phu Vuong ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Millimeter Wave ◽  
High Performance ◽  
Three Dimensional

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

Aerosol Jet® Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications

2011 ◽  
Vol 2011 (1) ◽  
pp. 001028-001032
Author(s):  
Michael J. O’Reilly ◽  
Jeff Leal ◽  
Suzette K. Pangrle ◽  
Kenneth Vartanian
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Three Dimensional ◽  
Contact Printing ◽  
Wire Bond ◽  
Printing System ◽  
3D Printed ◽  
Working Distance ◽  
Aerosol Jet Deposition ◽  
Vertical Interconnect

Aerosol Jet deposition systems provide an evolutionary alternative to both wire bond and TSV technology. As part of the Vertical Interconnect Pillar (ViP™) process, the Aerosol Jet system prints high density three-dimensional (3D) interconnects enabling multi-function integrated circuits to be stacked and vertically interconnected in high performance System-in-Packages (SiP). The stacks can include two or more die, with a total height of ∼ 2 millimeters. The non-contact printing system has a working distance of several millimeters above the substrate allowing 3D interconnects to be printed with no Z-height adjustments. The Aerosol Jet printhead is configured with multiple nozzles and a closely coupled atomizer to achieve production throughput of greater than 19,000 interconnects per hour. The Aerosol Jet printer deposits silver fine particle ink to form connections on staggered die stacks. High aspect ratio interconnects, less than 30-microns wide and greater than 6-microns tall, are printed at sub 60-micron pitch. After isothermal sintering at 150° C to 200° C for 30 minutes, highly conductive interconnects near bulk resistivity are produced. Pre-production yields exceeding 80% have been realized. This paper will provide further details on the 3D printed interconnect process, current and planned production throughput levels, and process yield and device reliability status.

Pre-Applied Inter Chip Fill for 3D-IC Chip Joining

2015 ◽  
Author(s):  
Yasuhiro Kawase ◽  
Makoto Ikemoto ◽  
Masaya Sugiyama ◽  
Hidehiro Yamamoto ◽  
Hideki Kiritani
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
High Performance ◽  
Three Dimensional ◽  
Conductive Filler ◽  
3D Ic ◽  
Fine Pitch ◽  
Silica Filler ◽  
Conductive Fillers ◽  
Process Compatibility

Three dimensional integrated circuits (3D-IC) have been proposed for the purpose of low power and high performance in recent years. Pre-applied inter chip fill is required for fine pitch interconnections, large chips, and also thin chips. In addition to them, pre-applied joining process with high thermal conductive inter chip fill (HT-ICF) is strongly required for the cooling of 3D-IC. Some kinds of matrix resins and thermal conductive fillers were simulated and evaluated for pre-applied ICF. As a result, matrix and cure agent appeared to be important to both pre-applied ICF process compatibility and thermal conductivity, so that we’d selected epoxy type matrix based on controlling super molecular structure due to its mesogen unit. And not only matrix but also filler appeared to be the key to improve thermal conductivity for pre-applied ICF at the same time. The thermal conductivity of conventional silica filler was only 1W/mK, so that, taking into account of thermal conductivity, density and its stability, we’d selected aluminum oxide and boron nitride as thermal conductive filler and optimized HT-ICF for pre-applied process. After composite was mixed and cured, some physical properties were measured and thermal conductivity was 1.8W/mK, CTE was below 21ppm/K and Tg was 120°C. Furthermore, new high thermal conductive filler was also studied. We’d synthesized completely new spherical BN (diameter <5um) and applied it to HT-ICF and the thermal conductivity was almost two times higher than conventional BN. In this study, we confirmed ICF physical characteristics and its pre-applied joining for 3D-IC and void-less joining was also discussed.

scholarly journals High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer

Nanomaterials ◽  
2020 ◽  
Vol 10 (11) ◽  
pp. 2145 ◽  
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Thin Film Transistor ◽  
Three Dimensional ◽  
Random Access ◽  
Oxide Thin Film ◽  
Amorphous Sio2 ◽  
Sio2 Substrate ◽  
Channel Layer

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (μFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, μFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2. The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2/SnO2 interfaces to increase the mobility. Such high μFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits

2016 ◽  
Vol 25 (11) ◽  
pp. 1650142 ◽  
Author(s):  
Kamineni Sumanth Kumar ◽  
John Reuben
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Three Dimensional ◽  
Buffer Insertion ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Tree Synthesis ◽  
3D Integrated Circuits ◽  
Tree Synthesis

Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of ‘More than Moore’ while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25–28% reduction in buffer count and 25–29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31–38% reduction in buffer count and 32–39% reduction in power.

scholarly journals TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Electronics ◽  
2018 ◽  
Vol 7 (7) ◽  
pp. 112 ◽  
Author(s):  
Wenchao Tian ◽  
Tianran Ma ◽  
Xiaohan Liu
Keyword(s):  
Integrated Circuits ◽  
Research Methods ◽  
Heavy Ions ◽  
High Performance ◽  
Ion Irradiation ◽  
Low Cost ◽  
Three Dimensional ◽  
Heavy Ion ◽  
High Energy ◽  
Radiation Environment

Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.

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