Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects

2013 ◽  
Vol 135 (3) ◽  
Author(s):  
Raphael Okereke ◽  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Cost Effective ◽  
Wafer Level ◽  
Mechanical Compliance ◽  
Interconnect Design ◽  
Compliant Interconnect ◽  
Thermomechanical Reliability ◽  
Interconnect Technology ◽  
Low K ◽  
Level Process

This paper presents a study on a dual-path compliant interconnect design which attempts to improve the balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Implementation of this interconnect technology can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermomechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermomechanical reliability of a dual-path compliant interconnect.

Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu IC’s

2006 ◽  
Author(s):  
Karan Kacker ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Dielectric Material ◽  
Semiconductor Industry ◽  
Cost Effective ◽  
Organic Substrate ◽  
Integrative Approach ◽  
Wafer Level ◽  
Technology Roadmap ◽  
Cte Mismatch ◽  
Compliant Interconnect ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnect are less likely to crack or delaminate the low-K dielectric material in current and future ICs. The interconnects are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we present an integrative approach which uses interconnects with varying compliance and thus varying electrical preformance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermo-mechanical reliability concerns. We also discuss the reliability assessment results of helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

2014 ◽  
Vol 2014 (1) ◽  
pp. 000599-000605 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Cost Effective ◽  
Disruptive Innovation ◽  
Design Rule ◽  
Wind Condition ◽  
Silicon Etching ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

2015 ◽  
Vol 12 (3) ◽  
pp. 111-117
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Integration ◽  
Cost Effective ◽  
Design Rule ◽  
Innovative Technology ◽  
Wind Condition ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

scholarly journals Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2370
Author(s):  
Xuanjie Liu ◽  
Qingqing Sun ◽  
Yiping Huang ◽  
Zheng Chen ◽  
Guoan Liu ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Cost Effective ◽  
Cmos Process ◽  
Semiconductor Technology ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Promising Solution ◽  
Leakage Failure ◽  
Wafer Level Package ◽  
Level Process

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.

Wafer Level Packaging Cost Modeling

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002312-002325 ◽  
Author(s):  
Chet A. Palesko
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Cost Effective ◽  
Circuit Board ◽  
Wafer Level ◽  
Design Rules ◽  
Wafer Level Packaging ◽  
Cost Effective Approach ◽  
Significant Difference ◽  
Interconnect Design

Wafer level packaging is often the most cost effective approach to achieve miniaturization. However, if it is used for the wrong application, it can be very expensive. The significant difference in printed circuit board interconnect design rules and semiconductor interconnect design rules must be addressed in any type of packaging approach, and presents unique challenges for wafer level packaging. If miniaturization is not required, this translation of semiconductor design rules to PCB design rules is most easily accomplished in a traditional wire bond package. However, when the package size and the die size must be the same, the package IO count is limited. Fanout WLP is an option to overcome the WLP IO restriction, but still achieve cost effective miniaturization. We will present the results of activity based cost and yield modeling of traditional wafer level packaging, fanout wafer level packaging, and flip chip packaging across a range of die sizes, package sizes, and defect densities. These results will show the most cost effective technology to match a variety of applications and package parameters.

Parallel-Path Compliant Structures as Electrical Interconnects

2010 ◽  
Author(s):  
Raphael Okereke ◽  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Cost Effective ◽  
Dielectric Materials ◽  
High Yield ◽  
Mechanical Reliability ◽  
Parallel Path ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Compliant Interconnect ◽  
Low K

The coefficient of thermal expansion (CTE) mismatch between a die and an organic substrate generates high stresses in the die when underfilled solder bumps are used. These high stresses could crack or delaminate low-K dielectric materials in the next-generation flip-chip devices. In addition to such on-chip failures, the solder interconnects could fail due to thermo-mechanical fatigue, especially when the interconnect dimensions are scaled down to meet fine-pitch requirements. To address these reliability issues, compliant interconnects have been proposed to alleviate the thermo-mechanical stresses in the chip assembly. Some of the challenges to be addressed with compliant interconnects are: higher electrical parasitic compared to solder bumps, cost-effective fabrication, and high-yield, fine-pitch assembly process. This paper presents a study on a parallel-path compliant interconnect design which attempts to balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Also, these interconnects can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermo-mechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermo-mechanical reliability of a parallel-path compliant interconnect.

Three-Mask Fabrication and Optimized Design of First-Level Free-Standing Interconnect for Microelectronics Application

2003 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Analytical Models ◽  
Optimized Design ◽  
Wafer Level ◽  
Free Standing ◽  
Mechanical Compliance ◽  
Compliant Interconnect ◽  
Free Solder

Advances in compliant off-chip interconnects have achieved great strides. G-Helix, an electroplated compliant chip-to-substrate interconnect has the potential for accomplishing low-cost, easy-to-fabricate, wafer-level packaging. In this work, the design, fabrication, optimization and reliability of the G-Helix compliant off-chip interconnects have been studied. A three-mask process was used to successfully fabricate the free-standing G-Helix compliant interconnect. The mechanical compliance and the electrical parasitics were studied through numerical and analytical models. Response Surface Methodology (RSM) was used to maximize the mechanical compliance and minimize the electrical parasitics as well as the stresses induced in the interconnect. It is also seen through the models that an array of interconnects will be able to withstand the die and the heat-sink weight without plastically yielding. Also, the G-Helix interconnect assembly on organic printed circuit board using lead-free solder will be able to withstand more than 1000 accelerated thermal cycles without the need for an underfill.

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