scholarly journals A High-Sensitivity and Low-Power Circuit for the Measurement of Abnormal Blood Cell Levels

2019 ◽  
Vol 29 (04) ◽  
pp. 2050061
Author(s):  
R. Nagulapalli ◽  
K. Hayatleh ◽  
S. Barker ◽  
A. A. Tammam ◽  
F. J. Lidgey ◽  
...  
Keyword(s):  
Blood Cell ◽  
Power Supply ◽  
Relaxation Oscillator ◽  
High Sensitivity ◽  
Cmos Technology ◽  
Readout Circuit ◽  
Digital Readout ◽  
Power Circuit ◽  
Silicon Area ◽  
Time Period

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter-Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65-nm CMOS technology and post-layout simulations show 15.25-aF sensitivity. The total circuit occupies 2,184-[Formula: see text]m2 silicon area and consumes 216[Formula: see text][Formula: see text]A from a 1-V power supply.

Effects of Preloading of Stannous Compounds on the Distribution of 99mTc-Pertechnetate

1977 ◽  
Vol 16 (01) ◽  
pp. 26-29 ◽  
Author(s):  
D. D. Greenberg ◽  
P. Som ◽  
G. E. Meinken ◽  
D. F. Sacker ◽  
H. L. Atkins ◽  
...  
Keyword(s):  
Blood Cell ◽  
Red Blood Cell ◽  
Plasma Ratio ◽  
99Mtc Pertechnetate ◽  
Time Period ◽  
Stannous Ion ◽  
Distribution Studies

Summary 99mTc-pertechnetate distribution studies were performed in rabbits and mice following pretreatment between 5—336 hours with various routinely used stannous complexes (HSA, MAA, GHT, DTPA, PYPs) containing different amounts of Sn++ (0.17 —15.0 μ mg/kg). Beyond a concentration of 0.26 mg/kg of Sn++ an alteration in 99mTc-pertechnetate distribution was observed. The red blood cell was found to be the most prominent target. An in-vivo reduction of 99mTc-pertechnetate apparently occurred by the presence of stannous ion within the red blood cell. Preloading time period between 5—24 hours did not alter the uptake of RBC/plasma ratio. Beyond that period it decreased slowly and still persisted up to 2 weeks following pretreatment. RBC/ plasma ratio of 99mTcO4 - increased with increased Sn++ content of various commercially available pharmaceutical kits.

scholarly journals 60–700 K CTAT and PTAT Temperature Sensors with 4H-SiC Schottky Diodes

Sensors ◽  
2021 ◽  
Vol 21 (3) ◽  
pp. 942
Author(s):  
Razvan Pascu ◽  
Gheorghe Pristavu ◽  
Gheorghe Brezeanu ◽  
Florin Draghici ◽  
Philippe Godignon ◽  
...  
Keyword(s):  
Low Cost ◽  
Schottky Diodes ◽  
Schottky Contact ◽  
High Sensitivity ◽  
Xrd Analysis ◽  
Absolute Temperature ◽  
Lower Sensitivity ◽  
Readout Circuit ◽  
Sensing Element ◽  
High Performing

A SiC Schottky dual-diode temperature-sensing element, suitable for both complementary variation of VF with absolute temperature (CTAT) and differential proportional to absolute temperature (PTAT) sensors, is demonstrated over 60–700 K, currently the widest range reported. The structure’s layout places the two identical diodes in close, symmetrical proximity. A stable and high-barrier Schottky contact based on Ni, annealed at 750 °C, is used. XRD analysis evinced the even distribution of Ni2Si over the entire Schottky contact area. Forward measurements in the 60–700 K range indicate nearly identical characteristics for the dual-diodes, with only minor inhomogeneity. Our parallel diode (p-diode) model is used to parameterize experimental curves and evaluate sensing performances over this far-reaching domain. High sensitivity, upwards of 2.32 mV/K, is obtained, with satisfactory linearity (R2 reaching 99.80%) for the CTAT sensor, even down to 60 K. The PTAT differential version boasts increased linearity, up to 99.95%. The lower sensitivity is, in this case, compensated by using a high-performing, low-cost readout circuit, leading to a peak 14.91 mV/K, without influencing linearity.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

scholarly journals Simulation and performance analysis of Multiple PCS sensors system

2017 ◽  
Vol 20 (2) ◽  
pp. 85
Author(s):  
Pawan Whig ◽  
Syed Naseem Ahmad ◽  
Surinder Kumar
Keyword(s):  
Low Cost ◽  
Reference Electrode ◽  
Oxygen Demand ◽  
High Sensitivity ◽  
Readout Circuit ◽  
Active Components ◽  
Multiple Sensors ◽  
Quality Of Water ◽  
Voltage Signal ◽  
And Performance

In this paper, a novel circuit is presented which overcome a serious limitation found in case of multiple sensors system. In this novel system design only one reference electrode and few active components used that makes the implementation of a low-cost system for the supervision of water quality. Photo Catalytic Sensor (PCS) estimates the parameter BOD (Biological Oxygen Demand) which is generally used to estimate quality of water. The system proposed in this paper involves a balanced bridge approach using few electronic components that provides a correlation in the input-output signals of low-cost sensors. The main reason of employing a readout circuit to PCS circuitry, is the fact that the fluctuation of O2 influences the threshold voltage, which is internal parameter of the FET and can manifest itself as a voltage signal at output but as a function of the trans conductance gain. The trans-conductance is a passive parameter and in order to derive voltage or current signal from its fluctuations the sensor has to be attached to readout circuit. This circuit provides high sensitivity to the changes in percentage of O2 in the solution.

scholarly journals A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications

2019 ◽  
Vol 28 (07) ◽  
pp. 1950110 ◽  
Author(s):  
K. Hayatleh ◽  
S. Zourob ◽  
R. Nagulapalli ◽  
S. Barker ◽  
N. Yassine ◽  
...  
Keyword(s):  
Biomedical Applications ◽  
High Performance ◽  
Impedance Measurement ◽  
Cmos Technology ◽  
Skin Impedance ◽  
Instrumentation Amplifier ◽  
Measurement Circuit ◽  
Silicon Area ◽  
The Impact ◽  
Mode Interference

This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high-frequency common mode interference. A modified three-OTA instrumentation amplifier (IA) has been proposed to help with the impedance measurement. Such systems offer a quick, noninvasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65[Formula: see text]nm CMOS technology and post-layout simulations confirm the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45[Formula: see text]uW from 1.5[Formula: see text]V power supply. The circuit occupies 0.01954[Formula: see text]mm2 silicon area.

An Analytical Study on Jitter Accumulation in Interleaved Phase Frequency Detectors for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 534 ◽  
pp. 197-205
Author(s):  
Kiichi Niitsu ◽  
Masato Sakurai ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Daiki Oki ◽  
...  
Keyword(s):  
Power Supply ◽  
Analytical Study ◽  
Cmos Technology ◽  
High Accuracy ◽  
Spice Simulation ◽  
Supply Noise ◽  
Noise Injection ◽  
Simulation Results ◽  
On Chip ◽  
Frequency Detector

This work presents the analytical study on jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. Jitter accumulation in phase frequency detector degrades the accuracy of on-chip jitter measurements, and required to be mitigated. In order to analyze and estimate the jitter accumulation in phase frequency detectors, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that, with a 50 mV power supply noise injection, jitter accumulation can be reduced from 1.03 ps to 0.49 ps (52% reduction) by using an interleaved architecture.

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