scholarly journals Ferroelectric HfO2-based materials for next-generation ferroelectric memories

2016 ◽  
Vol 06 (02) ◽  
pp. 1630003 ◽  
Author(s):  
Zhen Fan ◽  
Jingsheng Chen ◽  
John Wang
Keyword(s):  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Ferroelectric Materials ◽  
Oxide Semiconductor ◽  
Next Generation ◽  
New Class ◽  
Generation Cost ◽  
Potential Applications ◽  
Cost Efficient ◽  
Ferroelectric Memories

Ferroelectric random access memory (FeRAM) based on conventional ferroelectric perovskites, such as Pb(Zr,Ti)O3 and SrBi2Ta2O9, has encountered bottlenecks on memory density and cost, because those conventional perovskites suffer from various issues mainly including poor complementary metal-oxide-semiconductor (CMOS)-compatibility and limited scalability. Next-generation cost-efficient, high-density FeRAM shall therefore rely on a material revolution. Since the discovery of ferroelectricity in Si:HfO2 thin films in 2011, HfO2-based materials have aroused widespread interest in the field of FeRAM, because they are CMOS-compatible and can exhibit robust ferroelectricity even when the film thickness is scaled down to below 10 nm. A review on this new class of ferroelectric materials is therefore of great interest. In this paper, the most appealing topics about ferroelectric HfO2-based materials including origins of ferroelectricity, advantageous material properties, and current and potential applications in FeRAM, are briefly reviewed.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

RECENT PROGRESS OF FERROELECTRIC MEMORIES

2002 ◽  
Vol 12 (02) ◽  
pp. 315-323 ◽  
Author(s):  
HIROSHI ISHIWARA
Keyword(s):  
Recent Progress ◽  
Low Voltage ◽  
Random Access ◽  
Ferroelectric Materials ◽  
Basic Operation ◽  
Retention Characteristic ◽  
Low Voltage Operation ◽  
Cell Structures ◽  
Ferroelectric Memories ◽  
Non Destructive

Recent progress of ferroelectric random access memories (FeRAMs) is reviewed. First, novel ferroelectric materials, which are suitable for both low temperature crystallization and low voltage operation are introduced. Then, various cell structures in FeRAMs are discussed, in which particular attention is paid to non-destructive-readout-type cells such as a 1T-type cell composed of a single ferroelectric-gate field effect transistor. Finally, a novel 1T2C-type non-destructive-readout cell with good data retention characteristic is introduced and its basic operation is presented.

scholarly journals Electrical Characteristics of Nanoelectromechanical Relay with Multi-Domain HfO2-Based Ferroelectric Materials

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1208
Author(s):  
Chankeun Yoon ◽  
Changhwan Shin
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Ferroelectric Material ◽  
Ferroelectric Materials ◽  
Fabrication Process ◽  
Oxide Semiconductor ◽  
Electrical Characteristics ◽  
Switching Voltage ◽  
Capacitance Effect ◽  
Voltage Variation ◽  
Polycrystalline Structures

Since the discovery of ferroelectricity in HfO2-based materials which are comparable to the complementary metal-oxide–semiconductor (CMOS) fabrication process—a negative capacitance effect in the HfO2-based materials has been actively studied. Owing to nonuniform polarization-switching (which is originated from the polycrystalline structures of HfO2-based ferroelectric materials), the formation of multi-domains in the HfO2-based materials is inevitable. In previous studies, perovskite-based ferroelectric materials (which is not compatible to CMOS fabrication process) were utilized to improve the electrical properties of a nanoelectromechanical (NEM) relay. In this study, the effects of a multi-domain HfO2-based ferroelectric material on the electrical characteristics of an NEM relay were theoretically examined. Specifically, the number of domains, domain inhomogeneity and ferroelectric thickness of the multi-domain ferroelectric material were modulated and subsequently, its corresponding results were discussed. It was observed that the switching voltage variation was decreased with increasing the number of domains and decreasing domain inhomogeneity. In addition, the switching voltage was decreased with increasing ferroelectric thickness, owing to enhanced voltage amplification.

CNTFET-Based Memory Design

2020 ◽  
pp. 16-36
Author(s):  
Shashi Bala ◽  
Mamta Khosla ◽  
Raj Kumar
Keyword(s):  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Suitable Alternative ◽  
Memory Design ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Power ◽  
Effect Transistor

As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.

Sign in / Sign up

Export Citation Format

Share Document