scholarly journals Optimization of CNFET Parameters for High Performance Digital Circuits

2016 ◽  
Vol 2016 ◽  
pp. 1-9 ◽  
Author(s):  
Shimaa Ibrahim Sayed ◽  
Mostafa Mamdouh Abutaleb ◽  
Zaki Bassuoni Nossair
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Digital Circuits ◽  
Digital Circuit ◽  
Operating Voltage ◽  
Circuit Performance ◽  
Contact Materials ◽  
Strong Candidate ◽  
Power Delay Product ◽  
Near Future

The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. Therefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits.

scholarly journals Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling

2019 ◽  
Vol 4 (5) ◽  
pp. 575-579
Author(s):  
Gudala Konica . ◽  
Sreenivasulu Mamilla .
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Digital Circuits ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Future Generations ◽  
Power Delay Product

As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.

scholarly journals General Decomposition and Its Use in Digital Circuit Synthesis

VLSI Design ◽  
1995 ◽  
Vol 3 (3-4) ◽  
pp. 225-248 ◽  
Author(s):  
Lech Jóźwiak
Keyword(s):  
Design Methodology ◽  
Digital Circuits ◽  
Building Blocks ◽  
Digital Circuit ◽  
Structural Features ◽  
Logic Design ◽  
Circuit Synthesis ◽  
Abstraction Level ◽  
Microelectronic Technology ◽  
Complex Circuits

Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today's complex circuits and modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes the theory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be used for digital circuit synthesis. The decomposition methodology that is presented ensures “correctness by construction” and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structural features of the required information processing in relation to a given set of objectives and constraints.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals A multi-channel $$\varvec{H}_\infty $$ preview control approach to load alleviation design for flexible aircraft

2021 ◽  
Author(s):  
Ahmed Khalil ◽  
Nicolas Fezans
Keyword(s):  
Design Methodology ◽  
Control Design ◽  
Doppler Lidar ◽  
Preview Control ◽  
Reduced Order ◽  
Control Approach ◽  
Structural Fatigue ◽  
Trade Offs ◽  
Gust Load Alleviation ◽  
Near Future

AbstractGust load alleviation functions are mainly designed for two objectives: first, alleviating the structural loads resulting from turbulence or gust encounter, and hence reducing the structural fatigue and/or weight; and second, enhancing the ride qualities, and hence the passengers’ comfort. Whilst load alleviation functions can improve both aspects, the designer will still need to make design trade-offs between these two objectives and also between various types and locations of the structural loads. The possible emergence of affordable and reliable remote wind sensor techniques (e.g., Doppler LIDAR) in the future leads to considering new types of load alleviation functions as these sensors would permit anticipating the near future gusts and other types of turbulence. In this paper, we propose a preview control design methodology for the design of a load alleviation function with such anticipation capabilities, based on recent advancements on discrete-time reduced-order multi-channel $$H_\infty $$ H ∞ techniques. The methodology is illustrated on the DLR Discus-2c flexible sailplane model.

High-performance flexible redox supercapacitors induced by methylene blue with a wide voltage window

2018 ◽  
Vol 2 (2) ◽  
pp. 357-360 ◽  
Author(s):  
Chunmei Xu ◽  
Haiyan Wang ◽  
Jiang Deng ◽  
Yong Wang
Keyword(s):  
Methylene Blue ◽  
Solid State ◽  
High Performance ◽  
Porous Electrode ◽  
Operating Voltage ◽  
Solid State Electrolyte ◽  
Wide Operating

Coupling a porous electrode with methylene blue in a solid-state electrolyte resulted in high EDLC, wide operating voltage window, and enhanced faradaic pseudocapacitance.

Chlorophylls Contents in Echinocactus grusonii Extract

2014 ◽  
Vol 931-932 ◽  
pp. 1507-1511
Author(s):  
Nipha Chaicharoenaudomrung ◽  
Anant Oonsivilai ◽  
Ratchadaporn Oonsivilai
Keyword(s):  
High Performance ◽  
Reversed Phase ◽  
Lower Content ◽  
Chlorophyll Contents ◽  
Crude Extracts ◽  
Phytochemical Profile ◽  
Main Components ◽  
Near Future ◽  
Profile Study ◽  
Barrel Cactus

Currently, Golden Barrel cactus extract is formulated in dietary supplements, on account of its powerful weight loss profit and antioxidant activity. Golden Barrel cactus grusonii (Echinocactus grusonii), a Thai cultivar Golden Barrel cactus which is known as the golden barrel Golden Barrel cactus was therefore investigated for total chlorophylls with the aim of developing as a dietary supplement in future. The chlorophyll contents of 3 and 6 years Echinocactus grusonii extracts were evaluated by High Performance Liquid Chromatography with a Grace-Vydac 201TP54 reversed-phase polymeric C18 column. The results showed that chlorophyll a and chlorophyll b are the main components of Echinocactus grusonii crude extracts also at higher level at age 3 years. It was found that the main chlorophylls contents are chlorophyll a and chlorophyll b at 2.94±0.55μg/ml and 1.63±0.14 μg/ml for 3 years Echinocactus grusonii. In addition, the amount of chlorophyll a and chlorophyll b show lower content at 1.11±0.25μg/ml and 0.67±0.01μg/ml for 6 years Echinocactus grusonii. In conclusion, Echinocactus grusonii age 3 years crude extracts showed total chlorophylls contents higher than at age 6 years. The phytochemical profile study of Echinocactus grusonii age 3 years and 6 years crude extracts are planned in the near future.

Sign in / Sign up

Export Citation Format

Share Document