Low Power Ring Oscillator Design in 130nm CMOS Technology
2019 ◽
Vol 3
(3)
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pp. 14-18
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A temperature-stable, low-power ring oscillator design for implementation in an Application-Specific Integrated Circuit (ASIC) is presented. In this work, the design uses a new arrangement of chain delay elements consisting of a current-starved inverter and a CMOS capacitor. This power consumption improvement ring oscillator design was built in the environment of 130nm CMOS process technology using Mentor Graphics environment with voltage supply 1V. The simulation results show a maximum power consumption of 1.036 nW and it shows that the presented design is applicable in low power advanced sensing systems application including biomedical, chemical, and other sensors.
2020 ◽
Vol 9
(12)
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pp. 323-328
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2013 ◽
Vol 22
(10)
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pp. 1340033
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2020 ◽
Vol 17
(4)
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pp. 1595-1599
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2017 ◽
Vol MCSP2017
(01)
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pp. 7-10
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2010 ◽
Vol 19
(07)
◽
pp. 1609-1619
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