scholarly journals High-Efficiency DC–DC Converter with Charge-Recycling Gate-Voltage Swing Control

Energies ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 899 ◽  
Author(s):  
Jung-Duk Suh ◽  
Yeong-Ho Yun ◽  
Bai-Sun Kong
Keyword(s):  
Gate Voltage ◽  
Power Efficiency ◽  
High Efficiency ◽  
Cmos Technology ◽  
Test Chip ◽  
Efficient Manner ◽  
Light Load ◽  
Charge Recycling ◽  
Voltage Swing ◽  
Full Swing

This paper proposes a high-efficiency DC–DC converter with charge-recycling gate-voltage swing control with a light load. By achieving a variable gate-voltage swing in a very efficient manner by charge recycling, the power efficiency has been substantially improved due to the lower power consumption and the achieved balance between the switching and conduction losses. A test chip was fabricated using 65-nm CMOS technology. The proposed design reduces the gate-driving loss by up to 87.7% and 47.2% compared to the conventional full-swing and low-swing designs, respectively. The maximum power conversion efficiency was 90.3% when the input and output voltages are 3.3 V and 1.8 V, respectively.

scholarly journals Design of a Class-D Audio Amplifier With Analog Volume Control for Mobile Applications

2016 ◽  
Vol 62 (2) ◽  
pp. 187-196
Author(s):  
Karim El khadiri ◽  
Hassan Qjidaa
Keyword(s):  
Power Efficiency ◽  
High Efficiency ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Volume Control ◽  
Ramp Generator ◽  
Audio Amplifier ◽  
Class D ◽  
Level Shifter ◽  
Programmable Gain

Abstract A class-D audio amplifier with analog volume control (AVC) for portable applications is proposed in this paper. The proposed class-D consist of two sections. First section is an analog volume control which consists of an integrator, an analog MUX and a programmable gain amplifier (PGA). The AVC is implemented with three analog inputs (Audio, Voice, FM). Second section is a driver which consists of a ramp generator, a comparator, a level shifter and a gate driver. The driver is designed to obtain a low distortion and a high efficiency. Designed with 0.18 um 1P6M CMOS technology, the class-D audio amplifier with AVC achieves a total root-mean-square (RMS) output power of 0.5W, a total harmonic distortion plus noise (THD+N) at the 8-Ω load less than 0.06% and a power efficiency of 90% with a total area of 1.74 mm2.

scholarly journals A high-efficiency and compact charge pump with charge recycling scheme and finger boost capacitor

2019 ◽  
Vol 292 ◽  
pp. 01020
Author(s):  
Hui Peng ◽  
Pieter Bauwens ◽  
Herbert De Pauw ◽  
Jan Doutreloigne
Keyword(s):  
Power Supply ◽  
Power Efficiency ◽  
Output Voltage ◽  
High Efficiency ◽  
Charge Pump ◽  
Parasitic Capacitance ◽  
Chip Area ◽  
Charge Recycling ◽  
Compact Charge

A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. The proposed four-stage charge pump with finger capacitor can achieve 14.2 V output voltage from a 3 V power supply. The finger capacitor can increase the power efficiency of the charge pump to 60.5% and save chip area as well.

THE MULTILEVEL TECHNIQUE FOR IMPROVING FILTERLESS CLASS-D AUDIO AMPLIFIERS

2014 ◽  
Vol 23 (04) ◽  
pp. 1450047
Author(s):  
CHUN-WEI LIN ◽  
BING-SHIUN HSIEH
Keyword(s):  
Power Efficiency ◽  
Pulse Width Modulation ◽  
High Efficiency ◽  
Signal To Noise Ratio ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Multilevel Converter ◽  
Audio Amplifiers ◽  
Audio Amplifier ◽  
Class D

Class-D amplifier features very high efficiency on power delivery because its switching operation consumes tiny static power on very low on-resistance. In this work, a multilevel technique is presented to improve total-harmonic-distortion (THD) and signal-to-noise-ratio (SNR) of pulse-width-modulation (PWM) filterless class-D amplifiers. The proposed method consists of a multilevel converter and a time division adder (TDA) followed by PWM modulator. The PWM-modulated signal is arranged into several time divisions and then integrated and encoded to a set of parallel control signals for multilevel converter. Instead of the two-level PWM signal, the output signal of a multilevel converter is as stairway with less transient variation. The performance of THD and SNR are therefore improved because the instantaneous variation of signal is greatly reduced. To demonstrate the proposed method, a filterless audio amplifier was implemented by TSMC 5 V–0.35 μm CMOS technology. With 8 Ω speaker and 550 mW maximum power, experiment results show that the THD, SNR and power efficiency can be achieved over 0.02%, 85 dB and 85%, respectively.

scholarly journals Design of Multi Standard Near Field Communication Outphasing Transmitter with Modulation Wave Shaping

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 188
Author(s):  
Žiga Korošak ◽  
Nejc Suhadolnik ◽  
Anton Pleteršek
Keyword(s):  
Radio Frequency Identification ◽  
High Efficiency ◽  
Near Field ◽  
Cmos Technology ◽  
Near Field Communication ◽  
Differential Delay ◽  
Fully Differential ◽  
Delay Locked Loop ◽  
Modulation Wave ◽  
The Individual

The aim of this work is to tackle the problem of modulation wave shaping in the field of near field communication (NFC) radio frequency identification (RFID). For this purpose, a high-efficiency transmitter circuit was developed to comply with the strict requirements of the newest EMVCo and NFC Forum specifications for pulse shapes. The proposed circuit uses an outphasing modulator that is based on a digital-to-time converter (DTC). The DTC based outphasing modulator supports amplitude shift keying (ASK) modulation, operates at four times the 13.56 MHz carrier frequency and is made fully differential in order to remove the parasitic phase modulation components. The accompanying transmitter logic includes lookup tables with programmable modulation pulse wave shapes. The modulator solution uses a 64-cell tapped current controlled fully differential delay locked loop (DLL), which produces a 360° delay at 54.24 MHz, and a glitch-free multiplexor to select the individual taps. The outphased output from the modulator is mixed to create an RF pulse width modulated (PWM) output, which drives the antenna. Additionally, this implementation is fully compatible with D-class amplifiers enabling high efficiency. A test circuit of the proposed differential multi-standard reader’s transmitter was simulated in 40 nm CMOS technology. Stricter pulse shape requirements were easily satisfied, while achieving an output linearity of 0.2 bits and maximum power consumption under 7.5 mW.

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

scholarly journals Simulation of Drastic Lag Phenomena in GaAs-Based FETs for Large Voltage Swing

VLSI Design ◽  
2001 ◽  
Vol 13 (1-4) ◽  
pp. 245-249
Author(s):  
K. Horio ◽  
Y. Mitani ◽  
A. Wakabayashi ◽  
N. Kurosawa
Keyword(s):  
Surface State ◽  
Gate Voltage ◽  
Current Transient ◽  
Drain Voltage ◽  
Turn On ◽  
Voltage Swing

Turn-on characteristics of GaAs MESFETs and HEMTs are simulated when the gate voltage is changed abruptly. The gate-lag or slow current transient becomes more pronounced when the off-state gate voltage is more negative, because the surface-state effects or substrate-trap effects become more significant. Changes of I–V curves of GaAs MESFETs, when the drain voltage is swept with different speeds, are also simulated. When the swept time is short, the curve shows overshoot-like behavior and the kink disappears, indicating that the I–V characteristics should be quite different between DC and RF conditions.

scholarly journals Affordable and sustainable new generation of solar cells: calcium titanate (CaTiO3) - based perovskite solar cells

2018 ◽  
Vol 67 ◽  
pp. 01010
Author(s):  
Alfonsina Abat Amelenan Torimtubun ◽  
Anniza Cornelia Augusty ◽  
Eka Maulana ◽  
Lusi Ernawati
Keyword(s):  
Solar Cells ◽  
Power Efficiency ◽  
High Efficiency ◽  
Heating Temperature ◽  
Sol Gel ◽  
Perovskite Solar Cells ◽  
Calcium Titanate ◽  
Open Circuit ◽  
Raw Material ◽  
Lead Free

Indonesia is located along the equator lines with the high intensity of solar radiation averaging about 4.5 kWh of electrical energy/day. This potential leads to the selfsustaining energy possibility fulfilling the electricity needs. Due to their unique electronic structures and high-cost merit over the existing commercial PV technologies, perovskite solar cells (PSCs) have emerged as the next-generation photovoltaic candidate. Their highest power efficiency can be achieved of up to 22.1% in the last 5-6 years. However, this high efficiency came from CH3NH3PbI3 materials which contain lead, a toxic material. Herein calcium titanate (CT) as a lead-free perovskite material were synthesized through sintering of calcium carbonate (CaCO3) and titanium oxide (TiO2) by the sol-gel method. CT powders were characterized by SEM, XRF, FTIR and XRD then applied it onto the mesoporous heterojunction PSCs, with a device architecture ITO/TiO2/CaTiO3/C/ITO. By manipulating the raw material stoichiometry and heating temperature in the synthesis of CaTiO3, the device shows the highest power conversion efficiency (PCE) of 2.12%, shortcircuit current density (JSC) of 0.027 mA cm-2, open circuit voltage (VOC) of 0.212 V and fill factor (FF) of 53.90%. This sample can be an alternative way to create lead-free, largescale, and low-cost perovskite solar cells.

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

scholarly journals A –5 dBm 400MHz OOK Transmitter for Wireless Medical Application

2014 ◽  
Vol 60 (2) ◽  
pp. 193-198
Author(s):  
M. Yousefi ◽  
D. Koozehkanani ◽  
H. Jangi ◽  
N. Nasirzadeh ◽  
J. Sobhi
Keyword(s):  
Energy Consumption ◽  
Power Amplifier ◽  
High Efficiency ◽  
Medical Application ◽  
Cmos Technology ◽  
High Energy ◽  
Data Rate ◽  
High Data Rate ◽  
Low Power Consumption ◽  
High Data

Abstract A 400 MHz high efficiency transmitter for wireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies is proposed to achieve high data rate with low power consumption. In the on-off keying transmitters, the oscillator and power amplifier are turned off when the transmitter sends 0 data. The proposed class-e power amplifier has high efficiency for low level output power. The proposed on-off keying transmitter consumes 1.52 mw at -5 dBm output by 40 Mbps data rate and energy consumption 38 pJ/bit. The proposed transmitter has been designed in 0.18μm CMOS technology.

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

Sign in / Sign up

Export Citation Format

Share Document