scholarly journals Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages

Energies ◽  
2020 ◽  
Vol 13 (12) ◽  
pp. 3054
Author(s):  
Konstantin O. Petrosyants ◽  
Nikita I. Ryabov
Keyword(s):  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Software Tool ◽  
Thermal Design ◽  
Circuit Board ◽  
Processing Unit ◽  
Processor Time ◽  
3D Ic ◽  
Central Processing

The problem of thermal modeling of modern three-dimensional (3D) integrated circuit (IC) systems in packages (SiPs) is discussed. An effective quasi-3D (Q3D) approach of thermal design is proposed taking into account the specific character of 3D IC stacked multilayer constructions. The fully-3D heat transfer equation for global multilayer construction is reduced to the set of coupled two-dimensional (2D) equations for separate construction layers. As a result, computational difficulties, processor time, and RAM volume are significantly reduced, while accuracy can be provided. A software tool, Overheat-3D-IC, was developed on the base of the generalized Q3D package numerical model. For the first time, the global 3D thermal performances across the modern integrated circuit/through-silicon via/ball grid array (IC-TSV-BGA) and multi-chip (MC)-embedded printed circuit board (PCB) packages were simulated. A ten times decrease of central processing unit (CPU) time was achieved as compared with the 3D solutions obtained by commercial universal 3D simulators, while saving the sufficient accuracy. The simulation error of maximal temperature TMAX determination for different types of packages was not more than 10–20%.

High quality factor fractal inductor with complementary split-ring array inclusion

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 215-219
Author(s):  
Akhendra Kumar Padavala ◽  
Narayana Kiran Akondi ◽  
Bheema Rao Nistala
Keyword(s):  
Quality Factor ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Circuit Board ◽  
Integrated Circuit Design ◽  
Split Ring ◽  
Content Type ◽  
Practical Implications

Purpose This paper aims to present an efficient method to improve quality factor of printed fractal inductors based on electromagnetic band-gap (EBG) surface. Design/methodology/approach Hilbert fractal inductor is designed and simulated using high-frequency structural simulator. To improve the quality factor, an EBG surface underneath the inductor is incorporated without any degradation in inductance value. Findings The proposed inductor and Q factor are measured based on well-known three-dimensional simulator, and the results are compared experimentally. Practical implications The proposed method was able to significantly decrease the noise with increase in the speed of radio frequency and sensor-integrated circuit design. Originality/value Fractal inductor is designed and simulated with and without EBG surfaces. The measurement of printed circuit board prototypes demonstrates that the inclusion of split-ring array as EBG surface increases the quality factor by 90 per cent over standard fractal inductor of the same dimensions with a small degradation in inductance value and is capable of operating up to 2.4 GHz frequency range.

Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application

2012 ◽  
Vol 2012 (1) ◽  
pp. 001038-001045 ◽  
Author(s):  
Sheng-Tsai Wu ◽  
John H. Lau ◽  
Heng-Chieh Chien ◽  
Yu-Lin Chao ◽  
Ra-Min Tain ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Creep Strain ◽  
High Power ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Random Access ◽  
Circuit Board ◽  
3D Ic ◽  
Silicon Vias

In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of solder joints in the architecture is examined. The analyzed structure comprises one PCB (printed circuit board), one BT (bismaleimide triazene) substrate, one interposer with through silicon vias (TSVs), two DRAM (dynamic random access memory) chips and one high power ASIC (application specific integrated circuit) chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the Cu-filled TSV interposer.

scholarly journals A Behavioral DC Model of 3D Distributed Diodes in Presence of Wideband Microwaves on Active Substrate Boards

2020 ◽  
Author(s):  
Pragnan Chakravorty
Keyword(s):  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Circuit Board ◽  
Actual Behavior ◽  
Rf Components ◽  
Active Substrate ◽  
New Type ◽  
Dc Bias ◽  
Ic Technology

In the past few years, a new type of circuit board, named here as active substrate board (ASB), was introduced over circuit applications of diodes. Unlike a traditional printed circuit board (PCB), an ASB has its substrate made of a semiconductor. The inability of the traditional integrated circuit (IC) technology to integrate wavelength dependent radio frequency (RF) components triggered the advent of ASBs. These boards draw desirable features from IC as well as PCB technologies. Unprecedented challenges came up in modeling the different devices fabricated on an ASB owing to their large sizes and the presence of wideband microwaves. So far, modeling the effect of large sizes and ambient microwaves on DC bias of diodes have not been considered in scientific literature. Furthermore, the state of the art numerical simulators are unable to imitate the behavior of such diodes observed over measurements. Here, a semi-analytical, behavioral DC model of three dimensional (3D), distributed diodes on ASB is presented that is fairly accurate in predicting the actual behavior of the diodes. The model also opines a novel phenomenon of an AC affecting a DC with an added resistance.

scholarly journals A PCB Alignment System Using RST Template Matching with CUDA on Embedded GPU Board

Sensors ◽  
2020 ◽  
Vol 20 (9) ◽  
pp. 2736
Author(s):  
Minh-Tri Le ◽  
Ching-Ting Tu ◽  
Shu-Mei Guo ◽  
Jenn-Jier James Lien
Keyword(s):  
Template Matching ◽  
Printed Circuit Board ◽  
Vision System ◽  
Circuit Board ◽  
Processing Unit ◽  
Image Size ◽  
Central Processing ◽  
Matching Process ◽  
Alignment System ◽  
Alignment Process

The fiducial-marks-based alignment process is one of the most critical steps in printed circuit board (PCB) manufacturing. In the alignment process, a machine vision technique is used to detect the fiducial marks and then adjust the position of the vision system in such a way that it is aligned with the PCB. The present study proposed an embedded PCB alignment system, in which a rotation, scale and translation (RST) template-matching algorithm was employed to locate the marks on the PCB surface. The coordinates and angles of the detected marks were then compared with the reference values which were set by users, and the difference between them was used to adjust the position of the vision system accordingly. To improve the positioning accuracy, the angle and location matching process was performed in refinement processes. To overcome the matching time, in the present study we accelerated the rotation matching by eliminating the weak features in the scanning process and converting the normalized cross correlation (NCC) formula to a sum of products. Moreover, the scanning time was reduced by implementing the entire RST process in parallel on threads of a graphics processing unit (GPU) by applying hash functions to find refined positions in the refinement matching process. The experimental results showed that the resulting matching time was around 32× faster than that achieved on a conventional central processing unit (CPU) for a test image size of 1280 × 960 pixels. Furthermore, the precision of the alignment process achieved a considerable result with a tolerance of 36.4 μm.

Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)

2013 ◽  
Author(s):  
Leila Choobineh ◽  
Nick Vo ◽  
Trent Uehling ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Performance ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Electrical Current ◽  
Thermal Design ◽  
3D Ic ◽  
Thermal Models ◽  
3D Ics ◽  
And Performance

Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC. The experimental setup and procedure is described. Transient and steady-state measurements are made while heating the top die or the bottom die. Results indicate that passage of electrical current through the heaters in top/bottom die induces a measureable temperature rise. There appears to be a unique asymmetry in thermal performance between the top die and the bottom die. The top die is found to heat up faster and more than the bottom die. Results presented in this paper are expected to play a key role in validation of simulation-based and analytical thermal models for 3D ICs, and lead to a better fundamental understanding of heat transport in stacked systems. This is expected to lead to effective thermal design and characterization tools for 3D ICs.

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

2010 ◽  
Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Circuit Board ◽  
Discrete Component ◽  
Printed Circuit ◽  
Thermal Signature ◽  
Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Three Dimensional Detection of the via in the PCB CT Image Using Morphology Operation

2015 ◽  
Vol 752-753 ◽  
pp. 1406-1412
Author(s):  
Lei Zeng ◽  
Jian Chen ◽  
Han Ning Li ◽  
Bin Yan ◽  
Yi Fu Xu ◽  
...  
Keyword(s):  
Nondestructive Testing ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Detection Algorithm ◽  
Circuit Board ◽  
Dimensional Structure ◽  
Three Dimension ◽  
Shape Information ◽  
Printed Circuit ◽  
Testing Technology

In modern industry, the nondestructive testing of printed circuit board (PCB) can prevent effectively the system failure and is becoming more and more important. As a vital part of the PCB, the via connects the devices, the components and the wires and plays a very important role for the connection of the circuits. With the development of testing technology, the nondestructive testing of the via extends from two dimension to three dimension in recent years. This paper proposes a three dimensional detection algorithm using morphology method to test the via. The proposed algorithm takes full advantage of the three dimensional structure and shape information of the via. We have used the proposed method to detect via from PCB images with different size and quality, and found the detection performances to be very encouraging.

Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENTTM Software

2013 ◽  
Vol 795 ◽  
pp. 603-610 ◽  
Author(s):  
Mohamed Mazlan ◽  
A. Rahim ◽  
M.A. Iqbal ◽  
Mohd Mustafa Al Bakri Abdullah ◽  
W. Razak ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Fluid Dynamic ◽  
Three Dimensional ◽  
Circuit Board ◽  
Junction Temperature ◽  
Inlet Velocity ◽  
Chip Carrier ◽  
Flow Through ◽  
Package Density ◽  
Heat And Fluid Flow

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

scholarly journals FEM using projection of physical properties suitable for movement modeling and optimization processes

2020 ◽  
Vol 39 (5) ◽  
pp. 1185-1199
Author(s):  
Baptiste Ristagno ◽  
Dominique Giraud ◽  
Julien Fontchastagner ◽  
Denis Netter ◽  
Noureddine Takorabet ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Transient State ◽  
Mathematical Function ◽  
Processing Unit ◽  
Time Saving ◽  
Content Type ◽  
Central Processing ◽  
Cpu Time ◽  
Simple Geometry ◽  
Evaluation Time

Purpose Optimization processes and movement modeling usually require a high number of simulations. The purpose of this paper is to reduce global central processing unit (CPU) time by decreasing each evaluation time. Design Methodology Approach Remeshing the geometry at each iteration is avoided in the proposed method. The idea consists in using a fixed mesh on which functions are projected to represent geometry and supply. Findings Results are very promising. CPU time is reduced for three dimensional problems by almost a factor two, keeping a low relative deviation from usual methods. CPU time saving is performed by avoiding meshing step and also by a better initialization of iterative resolution. Optimization, movement modeling and transient-state simulation are very efficient and give same results as usual finite element method. Research Limitations Implications The method is restricted to simple geometry owing to the difficulty of finding spatial mathematical function describing the geometry. Moreover, a compromise between imprecision, caused by the boundary evaluation, and time saving must be found. Originality Value The method can be applied to optimize rotating machines design. Moreover, movement modeling is performed by shifting functions corresponding to moving parts.

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