Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation

2019 ◽  
Vol 29 (03) ◽  
pp. 2050038
Author(s):  
Mohammad Moradinezhad Maryan ◽  
Seyed Javad Azhari ◽  
Mehdi Ayat ◽  
Reza Rezaei Siahrood
Keyword(s):  
High Speed ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Saturation Region ◽  
Static Power ◽  
Linearity Error ◽  
Simulation Results ◽  
Compact Design ◽  
Four Quadrant

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Input Voltage ◽  
Voltage Reference ◽  
Analog Multiplier ◽  
Voltage Range ◽  
Voltage Variation ◽  
Static Power ◽  
Four Quadrant

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

High Frequency Unity Gain Buffer in 90-nm CMOS Technology

2016 ◽  
Vol 25 (07) ◽  
pp. 1650071
Author(s):  
Shuo Li ◽  
Xiaomeng Zhang ◽  
Saiyu Ren
Keyword(s):  
Harmonic Distortion ◽  
Low Frequency ◽  
Cmos Technology ◽  
Common Source ◽  
Active Load ◽  
Cmos Design ◽  
Saturation Region ◽  
Unity Gain ◽  
Unity Gain Buffer ◽  
Voltage Swing

A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

scholarly journals A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

Sensors ◽  
2020 ◽  
Vol 20 (11) ◽  
pp. 3303
Author(s):  
Jacek Jakusz ◽  
Waldemar Jendernalik ◽  
Grzegorz Blakiewicz ◽  
Miron Kłosowski ◽  
Stanisław Szczepański
Keyword(s):  
Harmonic Distortion ◽  
Low Frequency ◽  
Cmos Technology ◽  
Channel Length ◽  
Temperature Drift ◽  
Nanometer Cmos ◽  
Rail To Rail ◽  
Transconductance Amplifier ◽  
Current Converter ◽  
Linearity Error

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

NOVEL CMOS TECHNOLOGY-BASED LINEAR GROUNDED VOLTAGE CONTROLLED RESISTOR

2011 ◽  
Vol 20 (03) ◽  
pp. 447-455 ◽  
Author(s):  
ERKAN YUCE ◽  
SHAHRAM MINAEI ◽  
HALIL ALPASLAN
Keyword(s):  
Computer Simulation ◽  
Opposite Sign ◽  
Cmos Technology ◽  
The Body ◽  
Body Effect ◽  
Cmos Transistors ◽  
Current Voltage ◽  
Saturation Region ◽  
Simulation Results ◽  
Resistance Value

In this paper, a grounded voltage controlled resistor (GVCR) employing eight CMOS transistors, all of which are operating in saturation region, is proposed. The developed GVCR has two identical control voltages in opposite sign for electronically changing the resistance value. The linearity of the current-voltage (I - V) characteristic of the proposed GVCR is not affected by the body effect of the transistors. Computer simulation results with SPICE program are given to exhibit the performance and effectiveness of the introduced GVCR.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

2015 ◽  
Vol 19 ◽  
pp. 19-36 ◽  
Author(s):  
P.A. Gowri Sankar ◽  
G. Sathiyabama
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Field Effect ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Flash Adc ◽  
Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

scholarly journals Condition of phase angle for a new VDGA-based multiphase variable phase shift oscillator from 0o to 90o

2020 ◽  
Vol 10 (4) ◽  
pp. 3801
Author(s):  
Kasim K. Abdalla
Keyword(s):  
Phase Angle ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Electronic Control ◽  
Variable Phase ◽  
Voltage Mode ◽  
Condition Of Oscillation ◽  
Simulation Results ◽  
First Time ◽  
Modern Building

A novel interesting type of variable phase angle voltage mode oscillator using modern building block has been presented in this paper. The new proposed oscillator configuration which uses four voltage differencing gain amplifier (VDGA) and two grounded capacitors can generate two sinusoidal signals that change out of phase by 0 to 90 degree. It has four floating and explicit voltage mode outputs where every two outputs have the same phase. The circuit is characterized by (i) the condition of phase angle of the oscillation (PO) (this concept is introduced for the first time in this paper) can be tuned electronically (ii) the gain of the floating outputs can be controlled independently (iii) it provides electronic control of condition of oscillation (CO) and independent control of frequency of oscillation (FO). The Total Harmonic Distortion (THD) of the output waveforms was obtained and the results were reasonability values (less than 4.5%). The non-ideal analysis and simulation results are investigated and confirmed the theoretical analysis based upon VDGAs implementable in 0.35μm CMOS technology. Simulation results include time response and frequency response outputs generated by using the PSPICE program.

scholarly journals Simulation and manufacturing of modified circular monopole microstrip antenna for UWB applications

2021 ◽  
Vol 10 (1) ◽  
pp. 70
Author(s):  
Bilal S. Taha ◽  
Hamzah M. Marhoon
Keyword(s):  
Computer Simulation ◽  
Microstrip Antenna ◽  
High Speed ◽  
Reasonable Agreement ◽  
Ultra Wideband ◽  
Simulation Process ◽  
High Speed Data ◽  
Simulation Results ◽  
Compact Design ◽  
Uwb Applications

Ultra-wideband (UWB) technology is one of the most promising wireless communication solutions to be developed quickly because of the high-speed data, wide bandwidth and excellent immunity to multipath interference. In this work, the compact design of a modified circular monopole microstrip antenna is simulated and manufactured for the UWB applications. The simulation process of the proposed antenna was done based on the finite integration of the Computer Simulation Technology (CST) Microwave Studio (MWS). The proposed antenna comprises a copper radiating patch, Roger’s Kappa-438 substrate, and a single stub act as a reflector. The simulation results showed a reasonable agreement with the results of the measurement and good performance was achieved in the range from 1.8 to 10 GHz with VSWR less than 2.0.

scholarly journals A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator

2019 ◽  
Vol 9 (1S5) ◽  
pp. 41-44
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Delay Cell ◽  
Offset Voltage ◽  
Static Power ◽  
Cell Sample ◽  
Low Offset

Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5- bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5- bit ADC operates voltage at 1.8 volts and consumes an average power.

scholarly journals A Bulk-Driven Quasi-Floating Gate Regulated Cascode Current Mirror and Its Application in Squarer Circuit

2022 ◽  
Author(s):  
bchir bchir ◽  
Mounira Bchir ◽  
Imen Aloui ◽  
Nejib Hassen
Keyword(s):  
Performance Improvement ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Floating Gate ◽  
Input Current ◽  
Current Mirror ◽  
Transfer Error ◽  
Simulation Results ◽  
Cascode Current Mirror

Abstract A regulated cascode current mirror (RGC) and its improved version with bulk driven quasi floating gate technique (BD-QFG) are presented in this paper. The proposed BD-QFG RGC current mirror (CM) is compared with the conventional (GD) RGC CM to show the performance improvement. The conventional and unconventional CM are implemented in Candace Virtuoso using 90 nm CMOS technology. For input current (Iin) varied from 0 to 200 μA and for 0.8 V supply voltage, the simulation results present that the proposed BD-QFG RGC CM has less variation in current transfer error (0.2%) as compared to the GD RGC CM (12%). The output voltage requirement for 200 µA input current is respectively 0.7 V and 0.17 V for the GD RGC CM and the BD-QFG RGC CM. The power consumption of the proposed circuit is 22.71 μW which is 0.15 μW higher than the GD RGC (22.56 μW). The total harmonic distortion (THD) of the proposed circuit is 0.4% which is 1.1% less than the conventional circuit (1.5%). All these improvements in the proposed BD-QFG RGC CM are attained at a cost of 0.05 GHz reduction in frequency (2.31 GHz). The minimum supply voltage of BD-QFG RGC CM and GD RGC CM is 0.4 V and

An Efficient Architecture for Accurate and Low Power CMOS Analog Multiplier

2020 ◽  
pp. 2150045
Author(s):  
Tohid aghaei ◽  
Ali Naderi Saatlo
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
The Body ◽  
Body Effect ◽  
Low Power Dissipation ◽  
Low Power Cmos ◽  
Amplitude Modulator ◽  
Four Quadrant

A new analog four-quadrant multiplier in CMOS technology is proposed using translinear loops (TLs). The novelty of the work includes an improved structure resulting in high precision output, low power consumption and low body effect error. The higher accuracy is achieved using a symmetrical arrangement of the proposed multiplier, where the errors on the two sides of circuit are subtracted from each other. The simple structure, as well as the sharing bias branch in the squaring circuits, leads to the low power dissipation of the multiplier circuit. In addition, the proposed circuit is thoroughly analyzed in terms of the body effect error and the results are presented. In order to validate the performance of the circuit, the designed multiplier is used in two useful applications: frequency doubler and amplitude modulator. The post layout simulation results of the circuit are performed using Cadence Virtuoso and HSPICE with level 49 parameters (BSIM3v3) of TSMC 0.18[Formula: see text][Formula: see text]m technology. The results show a nonlinearity of 0.93%, a total harmonic distortion (THD) of 0.98% at a frequency of 1[Formula: see text]MHz, a [Formula: see text]3[Formula: see text]dB bandwidth of 736[Formula: see text]MHz and a maximum power dissipation of 0.0619[Formula: see text]mW.

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