scholarly journals Spatial Location in Integrated Circuits through Infrared Microscopy

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2175
Author(s):  
Raphaël Abelé ◽  
Jean-Luc Damoiseaux ◽  
Redouane El Moubtahij ◽  
Jean-Marc Boi ◽  
Daniele Fronte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Graph Matching ◽  
Silicon Layer ◽  
Spatial Location ◽  
Optical Microscope ◽  
Automated System ◽  
Infrared Microscopy ◽  
Speed Increase ◽  
Inexact Matching

In this paper, we present an infrared microscopy based approach for structures’ location in integrated circuits, to automate their secure characterization. The use of an infrared sensor is the key device for internal integrated circuit inspection. Two main issues are addressed. The first concerns the scan of integrated circuits using a motorized optical system composed of an infrared uncooled camera combined with an optical microscope. An automated system is required to focus the conductive tracks under the silicon layer. It is solved by an autofocus system analyzing the infrared images through a discrete polynomial image transform which allows an accurate features detection to build a focus metric robust against specific image degradation inherent to the acquisition context. The second issue concerns the location of structures to be characterized on the conductive tracks. Dealing with a large amount of redundancy and noise, a graph-matching method is presented—discriminating graph labels are developed to overcome the redundancy, while a flexible assignment optimizer solves the inexact matching arising from noises on graphs. The resulting automated location system brings reproducibility for secure characterization of integrated systems, besides accuracy and time speed increase.

An application of photoemission microscopy to failure analysis of complex silicon integrated circuits

1992 ◽  
Vol 50 (2) ◽  
pp. 1686-1687
Author(s):  
Danilo Golijanin
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Light Emission ◽  
Optical Microscope ◽  
Night Vision ◽  
Visible Range ◽  
Electron Hole ◽  
Polysilicon Gate ◽  
The Difference ◽  
Hole Recombination

Emission of visible light from forward and reverse biased silicon p-n junctions due to the radiative electron-hole recombination has been known since the mid-50s. The weak light emission was also seen from a silicon-dioxide dielectric in an integrated gate oxide capacitor formed between a polysilicon gate and an (n or p) well in an integrated circuit. The difference in carrier energies for each of these recombination mechanisms gives rise to a specific photon wavelength (energy) distribution in the visible range. All photoemitting events are characterized by a very low level light intensity due to the low quantum efficiency of about 10−5 - 10−4 photons per one electron-hole recombination.The first practical photoemission microscope was constructed by Khurana and Chiang. They took the advantage of the advances in night vision technology and used it for imaging the faint ("invisible") light coming from various silicon structures. A typical photoemission microscope consists of an x-y-z stage with the device holder, an optical microscope, a lightsensitive camera all set within a light-tight enclosure and a computer system for image acquisition and processing.

An Advanced Integrated Circuit Analysis System

2006 ◽  
Author(s):  
Edward Keyes ◽  
Jason Abt
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Optical Microscope ◽  
Circuit Analysis ◽  
Nanometer Scale ◽  
Automated Extraction ◽  
Analysis System ◽  
Detailed Circuit

Abstract Historically, the extraction of circuitry from an integrated circuit was normally within the abilities of the average FA laboratory and could be accomplished with little more than an optical microscope and film camera. Dramatic increases in the level of integration and number of metal interconnect levels coupled with shrinking feature sizes have rendered these techniques obsolete. This paper describes techniques and methods for the fast, semi-automated extraction of detailed circuit schematics from modern, nanometer scale integrated circuits.

Analysis of Integrated Circuits on the Scanning Electron Microscope

1972 ◽  
Vol 30 ◽  
pp. 484-485
Author(s):  
John J. Imai
Keyword(s):  
Integrated Circuits ◽  
High Power ◽  
Integrated Circuit ◽  
Optical Microscope ◽  
Visual Observation ◽  
Depth Of Field ◽  
List Type ◽  
Type Number ◽  
Mode Of Operation ◽  
Voltage Contrast

The SEM plays an important role in the performance of failure analyses of Integrated Circuits. As the complexity and density of electrical functions increases on the silicon chip, the more it is nescessary to analyze the detailed characteristics of the failed device. The types of failures of interest are those that have marginal or catastrophic performance characteristics and show no obvious visual defects.Three aspects of the SEM capabilities will be discussed.Standard high power magnification operationVoltage Contrast mode of operationEmission X-ray analysis operationVarious physical characteristics of an Integrated Circuit can be viewed on the SEM. These characteristics are difficult to view on a high power optical microscope due to the depth of field limitations. These characteristics include the following.Oxide stepsMetalization profile over oxide stepsWire bond analysisEtched metalization characteristicsThe Voltage Contrast mode of operation allows direct visual observation of electrical activity on the surface of the silicon chip.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

Micromechanics Measurements Applied to Integrated Circuit Microelectronics

1997 ◽  
Vol 473 ◽  
Author(s):  
David R. Clarke
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Fracture Resistance ◽  
Interface Fracture ◽  
New Techniques ◽  
Fracture Properties ◽  
Engineered Structures ◽  
Mechanical And Fracture Properties ◽  
Interconnect Lines ◽  
Metallic Interconnect

ABSTRACTAs in other engineered structures, fracture occasionally occurs in integrated microelectronic circuits. Fracture can take a number of forms including voiding of metallic interconnect lines, decohesion of interfaces, and stress-induced microcracking of thin films. The characteristic feature that distinguishes such fracture phenomena from similar behaviors in other engineered structures is the length scales involved, typically micron and sub-micron. This length scale necessitates new techniques for measuring mechanical and fracture properties. In this work, we describe non-contact optical techniques for probing strains and a microscopic “decohesion” test for measuring interface fracture resistance in integrated circuits.

Nanofabricated SiO2-Si-SiO2 Resonant Tunneling Diodes

2000 ◽  
Vol 631 ◽  
Author(s):  
J. G. Fleming ◽  
E. Chow ◽  
S.-Y. Lin
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Resonant Tunneling ◽  
Resonant Tunneling Diodes ◽  
Resonance Tunneling ◽  
Tunneling Diodes

ABSTRACTResonance Tunneling Diodes (RTDs) are devices that can demonstrate very highspeed operation. Typically they have been fabricated using epitaxial techniques and materials not consistent with standard commercial integrated circuits. We report here the first demonstration of SiO2-Si-SiO2 RTDs. These new structures were fabricated using novel combinations of silicon integrated circuit processes.

Automated Detection of Pin Defects on Counterfeit Microelectronics

2018 ◽  
Author(s):  
Pallabi Ghosh ◽  
Domenic Forte ◽  
Damon L. Woodard ◽  
Rajat Subhra Chakraborty
Keyword(s):  
Integrated Circuits ◽  
Depth Map ◽  
Optical Microscope ◽  
Automated Detection ◽  
Detection Methods ◽  
Global Supply Chains ◽  
Subject Matter Experts ◽  
Security Breaches ◽  
The Past ◽  
Skilled Subject

Abstract Counterfeit electronics constitute a fast-growing threat to global supply chains as well as national security. With rapid globalization, the supply chain is growing more and more complex with components coming from a diverse set of suppliers. Counterfeiters are taking advantage of this complexity and replacing original parts with fake ones. Moreover, counterfeit integrated circuits (ICs) may contain circuit modifications that cause security breaches. Out of all types of counterfeit ICs, recycled and remarked ICs are the most common. Over the past few years, a plethora of counterfeit IC detection methods have been created; however, most of these methods are manual and require highly-skilled subject matter experts (SME). In this paper, an automated bent and corroded pin detection methodology using image processing is proposed to identify recycled ICs. Here, depth map of images acquired using an optical microscope are used to detect bent pins, and segmented side view pin images are used to detect corroded pins.

The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits

2005 ◽  
Author(s):  
Mark Kimball
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Attenuation Factor ◽  
Cost Effective ◽  
Frequency Measurement ◽  
Single Frequency ◽  
Measurement Tool ◽  
Probe Design ◽  
Differential Measurement

Abstract This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

A Technique for Reliably Preparing Full-Length Metallographic Cross-Sections of Integrated Circuit Bond Wires

2006 ◽  
Author(s):  
Carl Nail
Keyword(s):  
Integrated Circuits ◽  
High Precision ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Radiographic Analysis ◽  
Good Resolution ◽  
Metallographic Preparation ◽  
Bond Wires ◽  
Darkfield Imaging ◽  
Bond Wire

Abstract To overcome the obstacles in preparing high-precision cross-sections of 'blind' bond wires in integrated circuits, this article proposes a different technique that generates reliable, repeatable cross-sections of bond wires across most or all of their lengths, allowing unencumbered and relatively artifact-free analysis of a given bond wire. The basic method for cross-sectioning a 'blind' bond wire involves radiographic analysis of the sample and metallographic preparation of the sample to the plane of interest. This is followed by tracking the exact location of the plane on the original radiograph using a stereomicroscope and finally darkfield imaging in which the wire is clearly visible with good resolution.

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