A New Triple-Slope Pipelined Time to Digital Converter by Stretching of Time

2015 ◽  
Vol 24 (09) ◽  
pp. 1550135 ◽  
Author(s):  
Mahdi Rezvanyvardom ◽  
Ebrahim Farshidi
Keyword(s):  
Dynamic Range ◽  
Circuit Complexity ◽  
Cmos Technology ◽  
Time Interval ◽  
Chip Area ◽  
Differential Nonlinearity ◽  
Novel Approach ◽  
Pvt Variations ◽  
Low Sensitivity ◽  
Time Stretching

This study investigates a novel approach for pipeline time-to-digital converters (TDCs) which employs analog interpolation and time stretching techniques for digitizing the time interval between two input signals as well as increasing resolution. In the proposed converter, analog interpolation is performed based on a triple-slope conversion. This converter will be a 9-bit pipeline TDC which contains three time stretching amplifiers (TSAs) and four 2.5-b/stage TDCs. This converter does not use delay lines in its structure. It features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations and high accuracy compared with the TDCs which have previously been proposed. Also, the time resolution, the dynamic range and the linear range of the TDC are improved. The proposed structure reduces the active chip area, the power consumption and the figure of merit (FoM). In addition, the integral nonlinearity (INL) and the differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the TDC is designed in TSMC 45-nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

Analysis and Design of a New 10-Bit High Accuracy and Resolution TDC by Elimination of Offset Voltage and Parasitic Capacitors Effects

2019 ◽  
Vol 28 (06) ◽  
pp. 1950095 ◽  
Author(s):  
Mahdi Rezvanyvardom ◽  
Amin Mirzaei
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
High Accuracy ◽  
Time Interval ◽  
Analysis And Design ◽  
Offset Voltage ◽  
Input Signals ◽  
Pvt Variations ◽  
Low Sensitivity ◽  
Comparator Offset

This paper investigates a time-to-digital converter (TDC) that employs interpolation and time stretching techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution. In the proposed TDC, interpolation is performed based on a dual-slope conversion. The proposed converter eliminates the comparator offset voltage error and the comparator parasitic capacitor error compared with the TDCs that have been proposed previously. The features of the converter consist of the high accuracy and high resolution due to elimination of errors and usage of the analog interpolation structure. Moreover, it does not use gated delay lines in its structure and has the advantage of low sensitivity to the temperature, power supply and process (PVT) variations. For validation, the proposed TDC is designed in TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology and simulated by Hspice simulator. The comparison between the theoretical and simulation results confirms the benefits of the proposed TDC operation. The results prove that it can be employed for high speed and resolution applications.

scholarly journals Receiver Designs for Electronic Toll Collection Systems : A Survey

2020 ◽  
pp. 576-581
Author(s):  
Rarika Ravi ◽  
Anu Assis
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Power Level ◽  
Cmos Technology ◽  
Electronic Toll Collection ◽  
Chip Area ◽  
Advantages And Disadvantages ◽  
Digitally Controlled ◽  
Toll Collection

<p>This paper discusses about different receiver designs adopted so far for various electronic toll collection systems. A comparative analysis based on the discussions is also provided. It shows that each design has it's own advantages and disadvantages compared to others. The main aim of this paper is to identify the most suitable design. The researches shows that the receiver design described in the 5.8GHz digitally controlled DSRC receiver for Chinese electronic toll collection system is the most suitable one. Here all RF, IF blocks and digital baseband for on-chip automatic gain control, are integrated on an RF-SoC. The proposed digitally controlled LNA and mixer circuits are elaborated. The technology used is 0.13μm CMOS technology. The RF block occupies a chip area of 0.75mm2. It consumes 22mA under a 1.5V supply voltage. The bit error rate maintains better than 10-6, the input power level varies from -75dBm to -8dBm. This design provides a receiver sensitivity improvement of at least 25%, and a dynamic range enhancement of at least 12%.</p>

A Low-Power High-Linear Time-to-Digital Converter for Measuring R-R Intervals in ECG Signal Optimized by Neural Network and TLBO Algorithm

2018 ◽  
Vol 28 (02) ◽  
pp. 1950021
Author(s):  
B. Ghanavati ◽  
E. Abiri ◽  
M. R. Salehi ◽  
N. Azhdari
Keyword(s):  
Neural Network ◽  
Dynamic Range ◽  
Linear Time ◽  
Optimization Method ◽  
Cmos Technology ◽  
Time Interval ◽  
Digital Converter ◽  
Two Stage ◽  
Time To Digital Converter ◽  
Tlbo Algorithm

In this paper, a two-stage time interpolation time-to-digital converter (TDC) is proposed to achieve adequate resolution and wide dynamic range for measuring R-R intervals in QRS detection. The architecture is based on a coarse counter and a couple of two-stage interpolator circuit in order to improve the conversion linearity. The proposed TDC is modeled with the neural network, while the teacher–learner-based optimization algorithm (TLBO) is used to optimize the integral nonlinearity (INL) of the proposed TDC. The proposed optimization method shows a characteristic close to the ideal output of the TDC behavior over a wide input range. Using the achieved results of the TLBO algorithm simulation results using CADENCE VIRTUOSO and standard 180[Formula: see text]nm CMOS technology shows 1.2[Formula: see text]s dynamic range, 100[Formula: see text]ns resolution, 0.19[Formula: see text]mW power consumption and area of 0.16[Formula: see text]mm2. The proposed circuit can find application in biomedical engineering systems and other fields where long and accurate time interval measurement is needed.

scholarly journals Novel Low-Complexity and Low-Power Flip-Flop Design

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 783
Author(s):  
Jin-Fa Lin ◽  
Zheng-Jie Hong ◽  
Chang-Ming Tsai ◽  
Bo-Cheng Wu ◽  
Shao-Wei Yu
Keyword(s):  
Low Power ◽  
Average Power ◽  
Circuit Complexity ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
System Level ◽  
Flip Flop ◽  
Chip Area

In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550086 ◽  
Author(s):  
Masoud Nazari ◽  
Leila Sharifi ◽  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Range ◽  
Logic Gates ◽  
Cmos Technology ◽  
Total Power ◽  
Current Steering ◽  
Domino Logic ◽  
Chip Area ◽  
Total Power Consumption

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

Design of Low Voltage Low Power ADC for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 561-566
Author(s):  
Si Kui Ren ◽  
Zhi Qun Li
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Chip Area ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter

2016 ◽  
Vol 25 (06) ◽  
pp. 1650066 ◽  
Author(s):  
Pantre Kompitaya ◽  
Khanittha Kaewdang
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Cmos Technology ◽  
Low Supply Voltage

A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.

A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION

2014 ◽  
Vol 23 (04) ◽  
pp. 1450053 ◽  
Author(s):  
FAN XIA ◽  
YIQIANG ZHAO ◽  
GONGYUAN ZHAO
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Differential Nonlinearity ◽  
Spurious Free Dynamic Range ◽  
Source Block ◽  
Current Steering Dac

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.

scholarly journals A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements

Sensors ◽  
2019 ◽  
Vol 19 (5) ◽  
pp. 1109 ◽  
Author(s):  
Jakub Szyduczyński ◽  
Dariusz Kościelnik ◽  
Marek Miśkowicz
Keyword(s):  
Successive Approximation ◽  
Circuit Complexity ◽  
Cmos Technology ◽  
Time Interval ◽  
Delay Lines ◽  
Quantization Step ◽  
Main Paper ◽  
The One ◽  
Asymmetrical Design ◽  
Single Set

The paper is focused on design of time-to-digital converters based on successive approximation (SA-TDCs—Successive Approximation TDCs) using binary-scaled delay lines in the feedforward architecture. The aim of the paper is to provide a tutorial on successive approximation TDCs (SA-TDCs) on the one hand, and to make the contribution to optimization of SA-TDC design on the other. The proposed design optimization consists essentially in reduction of circuit complexity and die area, as well as in improving converter performance. The main paper contribution is the concept of reducing SA-TDC complexity by removing one of two sets of delay lines in the feedforward architecture at the price of simple output decoding. For 12 bits of resolution, the complexity reduction is close to 50%. Furthermore, the paper presents the implementation of 8-bit SA-TDC in 180 nm CMOS technology with a quantization step 25 ps obtained by asymmetrical design of pair of inverters and symmetrized multiplexer control.

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

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