PERFORMANCE PARAMETERS OF LOW POWER SRAM CELLS: A REVIEW

2018 ◽  
Vol 6 (1) ◽  
pp. 25
Author(s):  
TIWARI NIDHI ◽  
NEEMA VAIBHAV ◽  
J RANGRA KAMAL ◽  
CHANDRA SHARMA YOGESH ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Performance Parameters

scholarly journals EVALUATION OF THE ROUTING METIRC W-METRIC USED WITH RPL PRTOCOL IN LLNS

2018 ◽  
Vol 19 (2) ◽  
pp. 80-89
Author(s):  
Rosminazuin Ab. Rahim ◽  
Abdallah Awad ◽  
Aisha Hassan Abdalla Hashim ◽  
ALIZA AINI MD RALIB
Keyword(s):  
Load Balancing ◽  
Low Power ◽  
Routing Protocol ◽  
Queue Length ◽  
Packet Delivery Ratio ◽  
Delivery Ratio ◽  
Performance Parameters ◽  
Lossy Networks ◽  
Promising Alternative ◽  
Packet Delivery

ABSTRACT: The current de-facto routing protocol over Low Power and Lossy Networks (LLN) developed by the IETF Working Group (6LOWPAN), is named as Routing Protocol for Low Power and Lossy networks (RPL). RPL in the network layer faces throughput  challenges due to the potential  large networks, number of nodes, and that  multiple  coexisting applications  will  be  running  in  the  same physical layer.  In this study, a node metric for RPL protocol based on the node’s Queue Backlogs is introduced, which leads to a better throughput performance while maintaining the delay and the ability to use with different network applications. This metric depends on the length of Packet Queue of the nodes with the consideration of other link and node metrics, like ETX or energy usage, leading to better load balancing in the network. To implement and evaluate the proposed metric compared to other RPL metrics, ContikiOS and COOJA simulator are used. Extensive simulations have been carried out in a systematic way resulting in a detailed analysis of the introduced metric namely W-metric, expected transmission count (ETX) and objective function zero (OF0) that uses hop-count as a routing metric. The analysis and comparison are based on five performance parameters, which are throughput, packet delivery ratio (PDR), latency, average queue length, and power consumption. Simulation results show that the introduced W-metric has a good performance compared to other RPL metrics with regards to performance parameters mentioned above. At the same time, the results show that its latency performance is comparable with other RPL routing metrics. In a sample simulation of 500 seconds with 25 nodes and with nodes sending packets periodically to the network root at a rate of 1 packet per 4 seconds, W-metric showed a very efficient throughput of 5.16 kbps, an increase of 8.2% compared to ETX. Results showed that it has a packet delivery ratio of 93.3%, which is higher compared to 83.3% for ETX and 74.2% for OF0. Average queue length of 0.48 packet shows improvement of 15.8% better than ETX. In addition, it exhibits an energy consumption of 5.16 mW which is 2.1% less than ETX. Overall, W-metric appears to be a promising alternative to ETX and OF0 as it selects routes that are more efficient by working on load balancing of the network and by considering the link characteristics. ABSTRAK: Protokol penghalaan de-facto semasa ke atas Rangkaian Kekuatan Rendah dan Lossy yang dibangunkan oleh Kumpulan Kerja IETF (6LOWPAN), dinamakan Protokol Penghalaan untuk Kekuatan Rendah dan Rugi (RPL). RPL dalam lapisan rangkaian menghadapi cabaran throughput berikutan jangkaan rangkaian besar, bilangan nod dan aplikasi berganda bersama akan diproses dalam lapisan fizikal yang sama. Dalam kajian ini, satu metrik nod untuk protokol RPL berdasarkan pada Backend Queue node diperkenalkan, yang membawa kepada prestasi yang lebih baik sambil mengekalkan kelewatan dan keupayaan untuk digunakan dengan aplikasi rangkaian yang berbeza. Metrik ini bergantung pada panjang Packet Queue dari node dengan pertimbangan metrik lain dan nodus lain, seperti ETX atau penggunaan tenaga, yang mengarah kepada keseimbangan beban yang lebih baik dalam rangkaian. Untuk melaksanakan dan menilai metrik yang dicadangkan berbanding metrik RPL lain, ContikiOS dan COOJA simulator telah digunakan. Simulasi meluas telah dijalankan dengan cara yang sistematik yang menghasilkan analisis terperinci mengenai metrik yang diperkenalkan iaitu W-metrik, kiraan penghantaran dijangkakan (ETX) dan fungsi objektif sifar (OF0) yang menggunakan kiraan hop sebagai metrik penghalaan. Analisis dan perbandingan adalah  berdasarkan lima parameter prestasi, iaitu throughput, nisbah penghantaran paket (PDR), latency, panjang panjang antrian, dan penggunaan kuasa. Hasil simulasi menunjukkan bahawa W-metrik yang diperkenalkan mempunyai prestasi yang lebih baik berbanding dengan metrik RPL lain berkaitan dengan parameter prestasi yang dinyatakan di atas. Pada masa yang sama, hasil menunjukkan bahawa prestasi latency W-metrik adalah setanding dengan metrik penghalaan RPL yang lain. Dalam simulasi sampel 500 saat dengan 25 nod dan dengan nod yang menghantar paket secara berkala ke akar rangkaian pada kadar 1 paket setiap 4 saat, W-metrik menunjukkan keluaran yang sangat efisien iaitu 5.16 kbps, peningkatan sebanyak 8.2% berbanding ETX. Keputusan menunjukkan bahawa ia mempunyai nisbah penghantaran paket 93.3%, yang lebih tinggi berbanding 83.3% untuk ETX dan 74.2% untuk OF0. Purata panjang giliran 0.48 packet menunjukkan peningkatan 15.8% lebih baik daripada ETX. Di samping itu, ia mempamerkan penggunaan tenaga sebanyak 5.16 mW iaitu 2.1% kurang daripada ETX. Secara keseluruhan, W-metrik nampaknya menjadi alternatif yang berpotensi menggantikan ETX dan OF0 kerana ia memilih laluan yang lebih cekap dengan bekerja pada keseimbangan beban rangkaian dan dengan mempertimbangkan ciri-ciri pautan.

Reversible Realization of 4-Bit Vedic Multiplier Circuit with Optimized Performance Parameters

2019 ◽  
Vol 17 (10) ◽  
pp. 826-831
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
High Speed ◽  
Digital Circuit ◽  
Performance Parameters ◽  
Low Loss ◽  
Vital Part ◽  
Multiplication Process ◽  
Vedic Multiplier ◽  
Multiplier Circuit

Low power high speed calculating devices are foremost requirement of this era. Moreover, multiplication is considered as the most vital part of any calculating system. Multiplication process is generally considered as the speed limiting process as it requires more time as compared to other basic arithmetic calculations. So, here we focus on multiplication calculation using vedic method. Moreover, Reversible realization of any digital circuit improves the performance of the system by reducing the power loss from it. Here, the concept of vedic multiplication and Reversible approach are combined to propose a 4-bit multiplier circuit with optimized performance parameters. Proposed design is also analyzed and compared with existing designs. This approach may be employed to propose other low loss devices.

scholarly journals The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

2022 ◽  
Author(s):  
Harshit Kansal ◽  
Aditya S Medury
Keyword(s):  
Low Power ◽  
Layer Thickness ◽  
Remnant Polarization ◽  
Design Space ◽  
Performance Parameters ◽  
Analog Performance ◽  
Wide Range ◽  
The Impact ◽  
Tcad Simulations ◽  
Mfis Structure

<div>In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.</div>

Power and area-efficient register designs involving EHO algorithm

Circuit World ◽  
2020 ◽  
Vol 46 (2) ◽  
pp. 93-105
Author(s):  
Neethu Anna Sabu ◽  
Batri K.
Keyword(s):  
Low Power ◽  
Building Blocks ◽  
Leakage Power ◽  
Shift Register ◽  
Total Power ◽  
Performance Parameters ◽  
Content Type ◽  
Total Power Consumption ◽  
First Time ◽  
Area Efficient

Purpose This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements. Design/methodology/approach The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm. Findings All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR). Originality/value The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

scholarly journals The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

2022 ◽  
Author(s):  
Harshit Kansal ◽  
Aditya S Medury
Keyword(s):  
Low Power ◽  
Layer Thickness ◽  
Remnant Polarization ◽  
Design Space ◽  
Performance Parameters ◽  
Analog Performance ◽  
Wide Range ◽  
The Impact ◽  
Tcad Simulations ◽  
Mfis Structure

<div>In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.</div>

scholarly journals A Noise Immune Double Suspended Gate MOSFET for Ultra Low-Power Applications

2021 ◽  
Author(s):  
Savio Jay Sengupta ◽  
Bijoy Goswami ◽  
Pritam Das ◽  
Subir Kumar Sarkar
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Accurate Result ◽  
Analytical Modelling ◽  
Experimental Result ◽  
Performance Parameters ◽  
Sharp Transition ◽  
Ultra Low Power ◽  
Pull Out ◽  
First Time

Abstract PurposeThe purpose of this paper is to develop the design and analytical modelling of a noise immune double suspended gate MOSFET (DSG-MOSFET) for ultra-low power applications. Also, Important performance parameters of the proposed structure such as pull-in and pull-out voltages have been thoroughly investigated with respect to the valuable structural parameters.MethodsThe design methodology used is EKV based analytical approach to calculate the pull-in and pull-out voltages with ingeniously developed boundary conditions which helps achieving reasonably accurate result. Also, the I-V characteristics has been modelled to justify accuracy.ResultsThe experimental result shows that the pull-in and pull-out voltages are in millivolts and microvolts range and hence it can be used in ultra-low power applications. As the ratio between the pull-out and the pull-in voltage is 10^(+3) range, justifies that the proposed structure is noise immune. The ID-VGS characteristic has hysteresis and this sharp transition in pull-in and pull-out voltage indicates that it can be used as an ideal switch with infinite sub-threshold slope.ConclusionThis paper presents a compact EKV based analytical modelling of pull-in and pull-out voltages for a DSG-MOSFET which predict the device characteristics reasonably similar to simulated results. Also, for the first time the noise immunity for a DSGMOSFET has been analyzed.

scholarly journals Analysis of Low Power Dynamic Comparator

2020 ◽  
Vol 9 (7) ◽  
pp. 329-332
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Low Power Consumption ◽  
Performance Parameters ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Static Power ◽  
Dynamic Comparators

Low power consumption, high performance dynamic comparators are widely used in high-speed Analog to Digital Converters (ADCs) and advanced input/output circuits. Mostly unique comparators utilize the latching stage thorough cross-coupled inverters, which gives a solid positive feedback, to fasten the comparison and reduce the static- power dissipation. In this paper, the analysis of dynamic comparators having best performance parameters in terms of power dissipation is presented. This is achieved by adopting low power techniques like adding transistors and sizing them to get efficient circuit. The proposed circuits are able to reduce power dissipation from 40-50%

Fault Tolerant Reversible Gate Based Sequential Quantum Dot Cellular Automata Circuits: Design and Contemplation

2020 ◽  
Vol 15 (3) ◽  
pp. 331-344 ◽  
Author(s):  
Rupali Singh ◽  
Devendra Kumar Sharma
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Cost Function ◽  
High Speed ◽  
Superior Performance ◽  
Performance Parameters ◽  
Quantum Dot Cellular Automata ◽  
Reversible Gate ◽  
Cost Efficient

In the era of quantum computing, Quantum Dot Cellular Automata (QCA) is a phenomenal technology which can produce low power, high speed and area efficient circuits. On the other hand, reversible logic is a promising paradigm which is used to construct low power circuits. This paper presents a design of a unique reversible gate based on QCA. This gate can facilitate the design of complex, cost efficient sequential circuits. The proposed gate is examined for various performance parameters such as realization of standard Boolean functions, cost function, energy dissipation and fault characterization. It is observed that the proposed gate exhibits superior performance as compared to the previously reported cost efficient designs in all the performance parameters. Furthermore, to evaluate the efficacy of the proposed QCA gate, reversible sequential latches are designed. The proposed structures of latches excel over the similar existing designs and have shown 50% improvement in latency, 58% improvement in effective cell area and around 70% improvement in cost function. The proposed latches are further investigated for temperature alterations to find the operating range of temperature for the circuits. The reversible QCA gate, proposed in this paper can be effectively used to design D latch, T latch, JK latch with improved performance. Hence, the proposed gate can find extensive scope in designing cost effective, low power, reversible sequential and combinational circuits.

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