Power and area-efficient register designs involving EHO algorithm

Circuit World ◽  
2020 ◽  
Vol 46 (2) ◽  
pp. 93-105
Author(s):  
Neethu Anna Sabu ◽  
Batri K.
Keyword(s):  
Low Power ◽  
Building Blocks ◽  
Leakage Power ◽  
Shift Register ◽  
Total Power ◽  
Performance Parameters ◽  
Content Type ◽  
Total Power Consumption ◽  
First Time ◽  
Area Efficient

Purpose This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements. Design/methodology/approach The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm. Findings All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR). Originality/value The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

Energy-efficient data retention in D flip-flops using STT-MTJ

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 229-241 ◽  
Author(s):  
Kanika Monga ◽  
Nitin Chaturvedi ◽  
S. Gurunarayanan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Power ◽  
Total Power ◽  
System State ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Content Type ◽  
Total Power Consumption ◽  
Standby Mode

Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

scholarly journals DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY

2013 ◽  
pp. 231-236
Author(s):  
FAYAZ KHAN ◽  
SIREESH BABU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Vital Role ◽  
Leakage Power ◽  
Total Power ◽  
Short Channel ◽  
Qualitative Comparison ◽  
Flip Flop ◽  
Low Area ◽  
Total Power Consumption

This paper enumerates design of D flip flop with low power and low area for low power applications, for that analysis of various D-flip flops for low power dissipation ,area and delays is carried out at 0.12um to achieve low power, low-area the technology is scaled down to nanometer ranges, due to shrinking process, the leakage power tends to play a vital role in total power consumption at nano meter technology. In this paper, different D flip flop circuits are designed using Berkeley Short Channel Insulated Gate MOSFET (BSIM4) model equations., in this paper to reduce leakage power at 90nm 70nm and 50nm we implement leakage power reduction techniques six techniques are considered they are namely Sleep transistor, sleepy stack, Dual sleep ,Dual stack Forced Transistor sleep (FTS) and Sleepy keeper From the results, it is observed that SLEEP TRANSISTOR, and SLEEPY KEEPER.FORCED TRANSISTOR SLEEP techniques produces lower power dissipation than the other techniques , in this paper a qualitative comparison is done with the help of Dsch,, Micro wind Simulation tools, this paper concludes that a leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

FLOORPLAN DESIGN WITH LOW POWER CONSIDERATIONS

1996 ◽  
Vol 07 (02) ◽  
pp. 305-322
Author(s):  
KAI-YUAN CHAO ◽  
D. F. WONG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Network Size ◽  
Total Power ◽  
Wire Length ◽  
Performance Requirements ◽  
Total Power Consumption ◽  
Distribution Of Power ◽  
The Cost

In this paper, a floorplanner for low power design is presented. Our objective is to optimize total power consumption and area during the selection and placement of various implementations for circuit modules. Furthermore, the proposed method considers performance requirements, power line noises, and distribution of power consumption in order to generate lower and evenly distributed power dissipation over the resulting circuit floorplan with a specified performance. For a set of benchmark circuits we tested, on the average, our floorplanner can achieve decreases of total power consumption, wire-length, and power/ground network size by 18.3%, 4.6%, and 24%, respectively, at the cost of an area increase of 8.8% when compared with an existing area/wire-length driven floorplanner.

scholarly journals A Hardware Approach of a Low-Power IoT Communication Interface by NXP FlexIO Module

2019 ◽  
Vol 25 (6) ◽  
pp. 35-39
Author(s):  
Libor Chrastecky ◽  
Jaromir Konecny ◽  
Martin Stankus ◽  
Michal Prauzek
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Total Power ◽  
Processing Unit ◽  
Embedded Devices ◽  
Communication Interface ◽  
Result Section ◽  
Central Processing ◽  
Total Power Consumption ◽  
Software And Hardware

This article describes implementation possibilities of specialized microcontroller peripherals, as hardware solution for Internet of Things (IoT) low-power communication, interfaces. In this contribution, authors use the NXP FlexIO periphery. Meanwhile, RFC1662 is used as a reference communication standard. Implementation of RFC1662 is performed by software and hardware approaches. The total power consumption is measured during experiments. In the result section, authors evaluate a time-consumption trade-off between the software approach running in Central Processing Unit (CPU) and hardware implementation using NXP FlexIO periphery. The results confirm that the hardware-based approach is effective in terms of power consumption. This method is applicable in IoT embedded devices.

scholarly journals Memristor: A Unique Discovery for Reducing Power

2020 ◽  
Vol 9 (4) ◽  
pp. 1183-1187
Keyword(s):  
Low Power ◽  
Dominant Role ◽  
Reducing Power ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Leakage Power ◽  
Total Power ◽  
Portable Devices ◽  
Power Devices ◽  
Threshold Regime

A Process parameter variation has increasing, which results unpredictable device behaviour, due to occurrence of deep submicron CMOS technology. As the time passage this issue is exasperated by low power requirements which are approaching transistor operation into sub threshold regime. Principally for portable devices efficient, capable and process variation amiable memory is the most demandable in the market. In designing of low power memories, leakage power is observant parameter to design low power devices, because leakage power plays a dominant role in the total power utilization of the devices. In this paper, simple 6T SRAM formed with memristor has compared with the technique based 6T SRAM for the various parameters like total power and leakage power

scholarly journals CMOS Operational Floating Current Conveyor Circuit for Instrumentation Amplifier Application

2020 ◽  
pp. 317-323
Author(s):  
Fahmi Elsayed ◽  
◽  
Mostafa Rashdan ◽  
Mohammad Salman
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Current Conveyor ◽  
Total Power ◽  
Low Power Consumption ◽  
Instrumentation Amplifier ◽  
Fully Integrated ◽  
Total Power Consumption ◽  
High Bandwidth ◽  
Operational Floating Current Conveyor

This paper presents a fully integrated CMOS Operational Floating Current Conveyor (OFCC) circuit. The proposed circuit is designed for instrumentation amplifier circuits. The CMOS OFCC circuit is designed and simulated using Cadence in TSMC 90 m technology kit. The circuit aims at two different design goals. The first goal is to design a low power consumption circuit (LBW design) while the second is to design a high bandwidth circuit (HBW design). The total power consumption of the LBW design is 1.26 mW with 30 MHz bandwidth while the power consumption of the HBW design is 3 mW with 104.6 MHz bandwidth.

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