scholarly journals Output Conductance of Line-TFETs for Different Device Parameters and its Effect on Basic Analog Circuits

2020 ◽  
Vol 15 (1) ◽  
pp. 1-7 ◽  
Author(s):  
Walter Gonçalez Filho ◽  
João Antonio Martino ◽  
Paula Ghedini Der Agopian
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Common Source ◽  
Gate Length ◽  
Current Mirrors ◽  
Conduction Mechanisms ◽  
The Impact ◽  
Output Conductance

This work addresses the impact of different device parameters on the analog characteristics of Line-Tunneling Field Effect Transistors (Line-TFETs). Source-to-drain separation, pocket thickness, pocket doping, gate-source alignment and the gate length are varied in order to evaluate their impact on the conduction mechanisms and on the overall transfer characteristics of the device. The variation of the main parameters responsible for device variability (pocket thickness and doping and gate-source alignment) is performed in order to analyze their impact on current mirrors, revealing that gate-source overlap improves the analog characteristics of the Line-TFET and that pocket doping should be limited to values smaller than 1018cm-3. Even though the drain current and the transconductance (gm) of this device are proportional to the gate area, simulations compared to experimental data show that the output conductance (gd) of Line-TFETs is practically independent of the gate length. The conduction mechanisms were analyzed through numerical simulations, revealing that this unique characteristic is due to source-to-drain tunneling, which defines the average value of gd on the saturation-like region and does not depend upon the gate length. The impact of this characteristic on analog circuit design is illustrated considering the example of a common-source stage and comparing its design when using MOSFET devices. This example reveals that the designer may choose whether to increase gm or gd in order to increase the circuit gain when using Line-TFETs, fundamentally differing from the MOSFET design.  

Insight into Channel Conduction Mechanisms of 4H-SiC(0001) MOSFET Based on Temperature-Dependent Hall Effect Measurement

2020 ◽  
Vol 1004 ◽  
pp. 620-626
Author(s):  
Hironori Takeda ◽  
Mitsuru Sometani ◽  
Takuji Hosoi ◽  
Takayoshi Shimura ◽  
Hiroshi Yano ◽  
...  
Keyword(s):  
Hall Effect ◽  
Field Effect ◽  
Elevated Temperatures ◽  
Field Effect Transistors ◽  
Free Carrier ◽  
Oxide Semiconductor ◽  
Thermal Excitation ◽  
Temperature Dependent ◽  
Conduction Mechanisms ◽  
The Impact

Temperature-dependent Hall effect measurements were conducted to investigate the channel conduction mechanisms of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). This method allows us to discriminate the impact of the density of mobile (free) carriers in the inversion channels and their net mobility on the performance of SiC MOSFETs. It was found that, while the free carrier ratio of SiC MOSFETs with conventional gate oxides formed by dry oxidation is below 4% at 300 K, increasing the free carrier ratio due to thermal excitation of trapped electrons from SiO2/SiC interfaces leads to an unusual improvement in the field-effect mobility of SiC MOSFETs at elevated temperatures. Specifically, a significant increase in free carrier density surpasses the mobility degradation caused by phonon scattering for thermally grown SiO2/SiC interfaces. It was also found that, although nitrogen incorporation in SiO2/SiC interfaces increases the free carrier ratio typically up to around 30%, introduction of an additional scattering factor associated with interface nitridation compensates for the moderate amount of thermally generated mobile carriers at high temperatures, indicating a fundamental drawback of nitridation of SiO2/SiC interfaces. On the basis of these findings, we discuss the channel conduction mechanisms of SiC MOSFETs.

scholarly journals Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 538
Author(s):  
Farhad Larki ◽  
Md Shabiul Islam ◽  
Arash Dehzangi ◽  
Mohammad Tariqul Islam ◽  
Hin Yong Wong
Keyword(s):  
Computer Aided Design ◽  
Three Dimensional ◽  
Drain Current ◽  
Channel Length ◽  
Influential Factors ◽  
Gate Length ◽  
Current Characteristics ◽  
Lateral Gate ◽  
The Impact ◽  
Gate Design

In this paper, we investigate the effect of lateral gate design on performance of a p-type double lateral gate junctionless transistors (DGJLTs) with an air gate gap. The impact of lateral gate length, which modifies the real channel length of the device and gate gap variation down to 50 nm which have been found to be the most influential factors in the performance of the device have been comprehensively investigated. The characteristics are demonstrated and compared with a nominal DGJLTs through three-dimensional technology computer-aided design (TCAD) simulation. At constant channel geometry (thickness and width), when the lateral gate length decreases, the results show constant flatband drain current characteristics while the OFF state current (IOFF) increases significantly. On the other hand, by decreasing the air gap the subthreshold current considerably decreases while the flatband current is constant. Moreover, at a certain gate gap, the gates lose control over the channel and the device simply works as a resistor. Electric field component, carriers’ density, band edge energies, and recombination rate of the carriers inside the channel in depletion and accumulation regimes are analysed to interpret the variation of output characteristics.

A Threshold Voltage Simulation of Hydrogen-Terminated Diamond MESFETs

2012 ◽  
Vol 482-484 ◽  
pp. 1093-1096 ◽  
Author(s):  
Xiao Feng Zhuang ◽  
Qing Kai Zeng ◽  
Bing Ren ◽  
Zhen Hua Wang ◽  
Yue Lu Zhang ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Diamond Film ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Diamond Surface ◽  
Gate Length ◽  
Simulation Results ◽  
Surface Conduction ◽  
Conduction Layer

In this paper, the threshold voltage of diamond film-based metal-semiconductor field effect transistors (MESFETs) has been simulated using Silvaco TCAD tools. The drain current (Id) versus gate voltage (Vg) relationship, and the distribution of acceptors in diamond surface conduction layer were also investigated. From the simulation results, it was found that the gate length contributed the most to the threshold voltage, while the doping depth almost had no impact on the threshold voltage value.

scholarly journals Nonlinearity Analysis of Quantum Capacitance and its Effect on Nano-Graphene Field Effect Transistor characteristics

2021 ◽  
Author(s):  
MUNINDRA MUNINDRA ◽  
DEVA NAND
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Charge Carrier Concentration ◽  
Single Layer Graphene ◽  
Quantum Capacitance ◽  
Large Area ◽  
Source Voltage ◽  
Current Calculation ◽  
The Impact

Abstract A simple, compact, and fundamental physics-based quasi-analytic model for Single layer graphene field effect transistors (GFETs) with large area graphene is presented in which the quantum mechanical density gradient method is utilised. The basic device physics of the two-dimensional (2D) graphene channel is studied analytically. This modeling leads to the precise drain current calculation of the GFETs. The drain current calculation for GFETs starts from charge carrier concentration, its density of states and quantum capacitance(QC). QC depends on the channel voltage as a function of gate to source voltage Vgs and drain to source voltage Vds primarily. The formulation of the drain current with velocity saturation has been done by the Monte Carlo simulation method. The performance of the analytical GFETs model is present the precise values of QC, its impact on drain current and transfer as well as output characteristics. The impact of QC at nanometer technology adds the nonlinearity to characteristics curves. The proposed method provides better results as compared with the previous analytical and simulated results.

scholarly journals Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019 ◽  
Vol 8 (2S6) ◽  
pp. 783-791
Keyword(s):  
Field Effect Transistors ◽  
Scaling Limit ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Length Variation ◽  
Gate Length ◽  
Double Gate ◽  
Simulation Design ◽  
Short Channel ◽  
Fully Depleted

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg ) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

The Impact of the Extrinsic Device on HFET Performance

1991 ◽  
Vol 240 ◽  
Author(s):  
David R. Greenberg ◽  
Jesús A. Del Alamo
Keyword(s):  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Insulator ◽  
Figures Of Merit ◽  
Velocity Saturation ◽  
Heterostructure Field Effect Transistors ◽  
Source Resistance ◽  
Carrier Velocity ◽  
The Impact ◽  
Ultimate Limit

ABSTRACTThe extrinsic device is known to degrade the performance of heterostructure field-effect transistors (HFET's) through the introduction of a parasitic source resistance (Rs). To date, however, there has been no recognition of the fact that carrier velocity saturation (vsat) can occur in both the extrinsic source and drain, setting the ultimate limit on maximum drain current (I,D,max) and on the useful VGS swing in HFET's. In this study, we demonstrate the mechanisms through which vsat in the extrinsic device limits device performance, using AlGaAs/n+-InGaAs Metal-Insulator-Doped-channel FET's (MIDFET's) as a vehicle. These devices show that gm falls at a lower VGSthan does fT, by as much as 1 V. This reveals that there are two mechanisms at work. The approach of vsat in the extrinsic source first causes the small-signal source resistance (Ts)to rise rapidly, leading gm to decline but leaving fT unaffected. As the carrier velocity in the extrinsic device approaches Vsat more closely, there is an actual decline of the carrier velocity in the intrinsic device. This process degrades velocity-related figures of merit such as and fT.

50nm Gate-Length Hydrogen Terminated Diamond Field Effect Transistors – Characterization and Inspection of Operation.

2011 ◽  
Vol 1282 ◽  
Author(s):  
David A. J. Moran ◽  
Donald A. MacLaren ◽  
Samuele Porro ◽  
Richard Hill ◽  
Helen McLelland ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Transmission Electron ◽  
Channel Effects ◽  
Physical And Chemical ◽  
Electron Energy Loss

ABSTRACTHydrogen terminated diamond field effect transistors (FET) of 50nm gate length have been fabricated, their DC operation characterised and their physical and chemical structure inspected by Transmission Electron Microscopy (TEM) and Electron Energy Loss Spectroscopy (EELS). DC characterisation of devices demonstrated pinch-off of the source-drain current can be maintained by the 50nm gate under low bias conditions. At larger bias, off-state output conductance increases, demonstrating most likely the onset of short-channel effects at this reduced gate length.

scholarly journals Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 27
Author(s):  
Jingtian Liu ◽  
Qian Sun ◽  
Bin Liang ◽  
Jianjun Chen ◽  
Yaqing Chi ◽  
...  
Keyword(s):  
Circuit Design ◽  
Analog Circuits ◽  
Analog Circuit ◽  
Forward Bias ◽  
Cmos Technology ◽  
Common Source ◽  
Single Event ◽  
Single Event Transient ◽  
Body Effect ◽  
Radiation Hardened

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

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