scholarly journals Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 538
Author(s):  
Farhad Larki ◽  
Md Shabiul Islam ◽  
Arash Dehzangi ◽  
Mohammad Tariqul Islam ◽  
Hin Yong Wong
Keyword(s):  
Computer Aided Design ◽  
Three Dimensional ◽  
Drain Current ◽  
Channel Length ◽  
Influential Factors ◽  
Gate Length ◽  
Current Characteristics ◽  
Lateral Gate ◽  
The Impact ◽  
Gate Design

In this paper, we investigate the effect of lateral gate design on performance of a p-type double lateral gate junctionless transistors (DGJLTs) with an air gate gap. The impact of lateral gate length, which modifies the real channel length of the device and gate gap variation down to 50 nm which have been found to be the most influential factors in the performance of the device have been comprehensively investigated. The characteristics are demonstrated and compared with a nominal DGJLTs through three-dimensional technology computer-aided design (TCAD) simulation. At constant channel geometry (thickness and width), when the lateral gate length decreases, the results show constant flatband drain current characteristics while the OFF state current (IOFF) increases significantly. On the other hand, by decreasing the air gap the subthreshold current considerably decreases while the flatband current is constant. Moreover, at a certain gate gap, the gates lose control over the channel and the device simply works as a resistor. Electric field component, carriers’ density, band edge energies, and recombination rate of the carriers inside the channel in depletion and accumulation regimes are analysed to interpret the variation of output characteristics.

scholarly journals Low cost digital fabrication approach for thumb orthoses

2017 ◽  
Vol 23 (6) ◽  
pp. 1020-1031 ◽  
Author(s):  
Miguel Fernandez-Vicente ◽  
Ana Escario Chust ◽  
Andres Conejero
Keyword(s):  
3D Printing ◽  
Computer Aided Design ◽  
Low Cost ◽  
Three Dimensional ◽  
Recovery Process ◽  
Digital Fabrication ◽  
Cost Comparison ◽  
Content Type ◽  
Custom Made ◽  
The Impact

Purpose The purpose of this paper is to describe a novel design workflow for the digital fabrication of custom-made orthoses (CMIO). It is intended to provide an easier process for clinical practitioners and orthotic technicians alike. It further functions to reduce the dependency of the operators’ abilities and skills. Design/methodology/approach The technical assessment covers low-cost three-dimensional (3D) scanning, free computer-aided design (CAD) software, and desktop 3D printing and acetone vapour finishing. To analyse its viability, a cost comparison was carried out between the proposed workflow and the traditional CMIO manufacture method. Findings The results show that the proposed workflow is a technically feasible and cost-effective solution to improve upon the traditional process of design and manufacture of custom-made static trapeziometacarpal (TMC) orthoses. Further studies are needed for ensuring a clinically feasible approach and for estimating the efficacy of the method for the recovery process in patients. Social implications The feasibility of the process increases the impact of the study, as the great accessibility to this type of 3D printers makes the digital fabrication method easier to be adopted by operators. Originality/value Although some research has been conducted on digital fabrication of CMIO, few studies have investigated the use of desktop 3D printing in any systematic way. This study provides a first step in the exploration of a new design workflow using low-cost digital fabrication tools combined with non-manual finishing.

Impact of Pulse Quenching Effect on Sensitive Area at Advanced Technologies

2013 ◽  
Vol 392 ◽  
pp. 693-696
Author(s):  
Wen Tao Xu ◽  
Yang Guo ◽  
Yan Kang Du
Keyword(s):  
Computer Aided Design ◽  
Three Dimensional ◽  
Sensitive Area ◽  
Isolation Technique ◽  
Quenching Effect ◽  
Advanced Technologies ◽  
Computer Aided ◽  
Simulation Results ◽  
Aided Design ◽  
The Impact

The impact of pulse quenching effect on the sensitive area is evaluated by using three-dimensional technology computer-aided design (TCAD) numerical simulation. Simulation results present that the pulse quenching effect could effectively reduce the sensitive area of PMOS transistors. By adopting the off-state gate isolation technique, the sensitive area is further reduced.

scholarly journals Output Conductance of Line-TFETs for Different Device Parameters and its Effect on Basic Analog Circuits

2020 ◽  
Vol 15 (1) ◽  
pp. 1-7 ◽  
Author(s):  
Walter Gonçalez Filho ◽  
João Antonio Martino ◽  
Paula Ghedini Der Agopian
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Common Source ◽  
Gate Length ◽  
Current Mirrors ◽  
Conduction Mechanisms ◽  
The Impact ◽  
Output Conductance

This work addresses the impact of different device parameters on the analog characteristics of Line-Tunneling Field Effect Transistors (Line-TFETs). Source-to-drain separation, pocket thickness, pocket doping, gate-source alignment and the gate length are varied in order to evaluate their impact on the conduction mechanisms and on the overall transfer characteristics of the device. The variation of the main parameters responsible for device variability (pocket thickness and doping and gate-source alignment) is performed in order to analyze their impact on current mirrors, revealing that gate-source overlap improves the analog characteristics of the Line-TFET and that pocket doping should be limited to values smaller than 1018cm-3. Even though the drain current and the transconductance (gm) of this device are proportional to the gate area, simulations compared to experimental data show that the output conductance (gd) of Line-TFETs is practically independent of the gate length. The conduction mechanisms were analyzed through numerical simulations, revealing that this unique characteristic is due to source-to-drain tunneling, which defines the average value of gd on the saturation-like region and does not depend upon the gate length. The impact of this characteristic on analog circuit design is illustrated considering the example of a common-source stage and comparing its design when using MOSFET devices. This example reveals that the designer may choose whether to increase gm or gd in order to increase the circuit gain when using Line-TFETs, fundamentally differing from the MOSFET design.  

On the Geometric Accuracy of RepRap Open-Source Three-Dimensional Printer

2015 ◽  
Vol 137 (10) ◽  
Author(s):  
Antonio Lanzotti ◽  
Domenico Maria Del Giudice ◽  
Antonio Lepore ◽  
Gabriele Staiano ◽  
Massimo Martorelli
Keyword(s):  
Open Source ◽  
Process Parameters ◽  
Computer Aided Design ◽  
Three Dimensional ◽  
Scientific Data ◽  
Correct Selection ◽  
Geometric Feature ◽  
Main Process ◽  
Geometric Features ◽  
The Impact

In the field of additive manufacturing (AM) processes, there is a significant lack of scientific data on the performance of open-source 3D printers in relation to process parameter values. The purpose of this paper is to assess the impact of the main process parameters on the accuracy of a set of typical geometric features, as obtained with an open-source 3D printer, the RepRap Prusa-Mendel I2. For this purpose, a benchmarking part was set up, composed of elementary shapes, representing a series of different geometric features. By means of a DoE approach, it was possible to assess the effects of two process parameters—layer thickness (Lt) and flow rate (Fr)—on five geometric features: cube, sphere, cylinder, cone, and angled surface. A high resolution Laser Scanner was used to evaluate the variation between the acquired geometric feature and the corresponding 3D computer-aided design (CAD) nominal model. On the basis of experimental results, it was possible to analyze and discuss the main effects of the above-mentioned process parameters on each geometric feature. These results can help RepRap users in the correct selection of process parameters with the aim of improving the quality of prototypes.

scholarly journals Revisiting Healing Environments: Islamic Interior Elements in Hospital Rooms in North Africa

2021 ◽  
pp. 193758672110423
Author(s):  
Moamer M. Gashoot
Keyword(s):  
Interior Design ◽  
User Satisfaction ◽  
Computer Aided Design ◽  
Medical Center ◽  
Three Dimensional ◽  
Quality Of Healthcare ◽  
Hospital Room ◽  
Patient Health ◽  
A Prospective Study ◽  
The Impact

Background: A predominant notion among researchers is that hospital room design and decor are subject to the designer’s expression of self, which is contrary to evidence-based studies showing that design and decor can impact patient health. The aim of this study was to examine whether improvement in quality of healthcare provided in hospitals could be achieved through the convergence of expertise of healthcare professionals and hospital room designers. Methods: This was a prospective study to identify the impact of hospital interior design features with a focus on single occupancy rooms. Volunteers were recruited through advertisements and the study was conducted at the Tripoli Medical Center. Responses were analyzed using a three-dimensional computer-aided design software to help respondents accurately map their preferences and visualize outcomes. Results: Participants preferred an aesthetically pleasing hospital room environment that included art and bright colors, window views, and the need for personalization, technology, mobility, and flexibility, all of which improved satisfaction and happiness. Of these, participants’ preference for technology as a cause for satisfaction and happiness was a novel finding. Conclusion: Designers of hospital room interiors should plan and create an appealing single occupancy room for increasing user satisfaction and patient wellness.

Effects of Device Architecture on the Performance of Organic Thin Film Transistors

2008 ◽  
Vol 1138 ◽  
Author(s):  
Xiaojing Zhou ◽  
Karyn E. Mutkins ◽  
Daniel Elkington ◽  
Kathleen Sirois ◽  
Warwick Belcher ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Drain Current ◽  
Channel Length ◽  
Device Performance ◽  
Organic Thin Film ◽  
Organic Thin Film Transistor ◽  
Device Architecture ◽  
Electrochemical Transistor ◽  
The Impact

AbstractThe impact of device dimension and architecture on the device performance of an all–solution fabrication organic thin film transistor (OTFT) has been investigated. The saturation drain current is inversely proportional to the channel length, indicating that a characteristic of field–effect like transistor has been obtained. In contrast, the drain current is independent of the thickness of polyvinylphenol (PVP) dielectric layer and a large leakage current is observed at the gate electrode indicating that the device also shows electrochemical transistor characteristics. Although separate conductance measurements of a single poly(3–hexylthiophene) (P3HT) layer and a P3HT/PVP layer reveal that the conductance is proportional to the thickness of the layer, the maximum achieved drain current in the fabricated OTFT is inversely proportional to the P3HT thickness. Using this data, an interface of P3HT/PVP or a maximum P3HT thickness for a working transistor of approximately 160 ± 16 nm can be extracted. The mechanism of operation of these devices is discussed.

Analysis of OSB Mat Structure Using CAD Technology

2010 ◽  
Vol 113-116 ◽  
pp. 1619-1623
Author(s):  
Peng Li ◽  
Yu Bo Tao ◽  
Feng Hu Wang ◽  
Sun Guo Wang
Keyword(s):  
Computer Aided Design ◽  
Structural Characteristics ◽  
Three Dimensional ◽  
Three Dimensional Model ◽  
Forming Process ◽  
Strand Orientation ◽  
Realistic Description ◽  
Relationship Of ◽  
The Impact ◽  
The Relationship

For further researching the structural characteristics of Orientated strand board (OSB) mat, a three-dimensional model was developed using computer-aided design (CAD) technology to simulate behaviors of individual strands in the mat-forming process. This model provided a more realistic description of the mat structure than the previous simulations in using varied strand geometry and different types of strand orientation, defining strand location, and solving the problem of edge effect. This model can be used to analyze the impact of strand orientation on the number of strand overlaps, and to identify the relationship of strand orientation and the horizontal voids distribution in the mat. Information provided by this model is the basis of further studying the effect of the mat formation on panel void characteristics, and the relationship of the voids volume to panel properties.

scholarly journals Effects of Proton Irradiation on the Current Characteristics of SiN-Passivated AlGaN/GaN MIS-HEMTs Using a TMAH-Based Surface Pre-Treatment

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 864
Author(s):  
Young Jun Yoon ◽  
Jae Sang Lee ◽  
Jae Kwon Suk ◽  
In Man Kang ◽  
Jung Hee Lee ◽  
...  
Keyword(s):  
Proton Irradiation ◽  
Surface States ◽  
Drain Current ◽  
Radiation Hardness ◽  
Ambient Atmosphere ◽  
High Electron ◽  
Hydrogen Passivation ◽  
Pre Treatment ◽  
Current Characteristics ◽  
The Impact

This study investigated the combined effects of proton irradiation and surface pre-treatment on the current characteristics of Gallium Nitride (GaN)-based metal-insulator-semiconductor high-electron-mobility-transistors (MIS-HEMTs) to evaluate the radiation hardness involved with the Silicon Nitride (SiN) passivation/GaN cap interface. The impact of proton irradiation on the static and dynamic current characteristics of devices with and without pre-treatment were analyzed with 5 MeV proton irradiation. In terms of transfer characteristics before and after the proton irradiation, the drain current of the devices without and with pre-treatment were reduced by an increase in sheet and contact resistances after the proton irradiation. In contrast with the static current characteristics, the gate-lag characteristics of the device with pre-treatment were significantly degenerated. In the device with pre-treatment, the hydrogen passivation for surface states of the GaN cap was formed by the pre-treatment and SiN deposition processes. Since the hydrogen passivation was removed by the proton irradiation, the newly created vacancies resulted in the degeneration of gate-lag characteristics. After nine months in an ambient atmosphere, the gate-lag characteristics of the device with pre-treatment were recovered because of the hydrogen recombination. These results demonstrated that the radiation hardness of MIS-HEMTs was affected by the SiN/GaN interface quality.

scholarly journals Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

2019 ◽  
Vol 9 (4) ◽  
pp. 2863
Author(s):  
K. E. Kaharudin ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
Ameer F. Roslan
Keyword(s):  
Process Design ◽  
Concentration Level ◽  
Drain Current ◽  
Channel Length ◽  
Electrical Performance ◽  
Double Gate ◽  
Electrical Characteristics ◽  
Metal Gate ◽  
The Impact ◽  
Gate Work Function

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

Impact of Thermal Sub-Continuum Effects on Electrical Performance of Silicon-on-Insulator Transistors

2005 ◽  
Author(s):  
Keivan Etessam-Yazdani ◽  
Rozana Hussin ◽  
Mehdi Asheghi
Keyword(s):  
Thermal Resistance ◽  
Drain Current ◽  
Silicon On Insulator ◽  
Electrical Performance ◽  
Gate Length ◽  
Boundary Scattering ◽  
Self Heating ◽  
Soi Devices ◽  
The Impact ◽  
Channel Region

In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. Effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated into a electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of gate length and silicon layer thickness. The device thermal resistance is increased by nearly a factor of 3 due to the scaling of gate length from 180nm to 10nm. Self-heating in SOI devices with gate length of 10nm can be responsible for up to 30% reduction in the saturation current and neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two.

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