scholarly journals Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

2020 ◽  
Vol 15 (2) ◽  
pp. 1-5
Author(s):  
Vinicius Vono Peruzzi ◽  
William Cruz ◽  
Gabriel Augusto Da Silva ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Silicon Germanium ◽  
Field Effect Transistors ◽  
Alpha Angle ◽  
Cmos Technology ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
X Rays ◽  
Length Effect ◽  
Corner Effect

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

2019 ◽  
Vol 14 (2) ◽  
pp. 1-8
Author(s):  
Egon Henrique Salerno Galembeck ◽  
Denis Flandre ◽  
Christian Renaux ◽  
Salvador Pinillos Gimenez
Keyword(s):  
High Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Soi Mosfet ◽  
Temperature Conditions ◽  
Channel Lengths

This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions.  To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

scholarly journals Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs Shaded Conditions

2020 ◽  
Vol 24 (1) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Prabir Saha
Keyword(s):  
Integrated Circuits ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Cmos Technology ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Analytical Models ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects

Nowadays, the endlessly increasing demand for faster and complex integrated circuits (IC) has been fuelled by the scaling of metal-oxide-semiconductor field-effect-transistors (MOSFET) to smaller dimensions. The continued scaling of MOSFETs approaches its physical limits due to short-channel effects (SCE). Double-gate (DG) MOSFET is one of the promising alternatives as it offers better immunity towards SCEs and can be scaled to the shortest channel length. In future, ICs can be designed using DG-CMOS technology for which mathematical models depicting the electrical characteristics of the DG MOSFETs are foremost needed. In this paper, a review on n-type symmetric DG MOSFETs models has been presented based on the analyses of electrostatic potential distribution, threshold voltage, and drain-current models. Mathematical derivations of the device models are described elaborately, and numerical simulations are also carried out to validate the replicability of models.

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Wong How Hwan ◽  
Vinny Lam Siu Fan ◽  
Yusmeeraz Yusof
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dna Hybridization ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Channel Length ◽  
Electrical Signal ◽  
Oxide Semiconductor ◽  
Detection Circuit

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool. 

scholarly journals Static and dynamic modeling of organic thin film transistors: effect of channel length on the Mayer–Neldel rule energy and quasistatic capacitances

2018 ◽  
Vol 81 (3) ◽  
pp. 30202 ◽  
Author(s):  
Nawel Arfaoui ◽  
Walid Boukhili ◽  
Mounira Mahdouani ◽  
Joaquim Puigdollers ◽  
Ramzi Bourguiga
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Organic Thin Film ◽  
Length Effect ◽  
Transmission Line Method ◽  
Effect Transistor ◽  
Overall Resistance ◽  
Channel Lengths

In this work, pentacene based thin film transistors (TFTs) with different channel lengths (L = 2.5, 5, 10 and 20 μm) have been fabricated and characterized electrically. Exploiting the electrical characteristics, we have analyzed the channel length effect on the key parameters of fabricated TFTs. We found that the performance of pentacene-TFTs was enormously enhanced by the reduction of channel length .We have also examined the influence of contact and channel resistances (RC and Rch) on the electrical proprieties of fabricated TFTs, using the transmission line method (TLM). Then, we have modeled the dependence of the total resistance RT on the gate voltage VG using the grain boundary trapping Meyer–Neldel rule (GBT-MNR) model and we have successfully reproduced, the output characteristic of pentacene TFTs using the overall resistance extracted from the GBT-MNR model. Finally, in order to investigate the channel length effect on the dynamic behavior of fabricated devices, we have reported a dynamic model based on the quasistatic assumptions which were used for metal-oxide-semiconductor field-effect transistor (MOSFET). Accordingly, we have presented a simple small-signal equivalent circuit to calculate theoretically the capacitances of pentacene-TFTs for different channel lengths.

DIELECTRIC AND INTERFACE STABILITY OF LaSmO3 FILMS

2012 ◽  
Vol 19 (06) ◽  
pp. 1250064 ◽  
Author(s):  
WEITAO SU ◽  
QIUHUI ZHUANG ◽  
DEXUAN HUO ◽  
BIN LI
Keyword(s):  
Band Gap ◽  
Leakage Current ◽  
Silicon Germanium ◽  
Field Effect Transistors ◽  
Attenuated Total Reflection ◽  
Oxide Semiconductor ◽  
Thermal Stabilities ◽  
Xps Spectra ◽  
X Ray ◽  
High K

The continuous downscaling of metal oxide semiconductor field effect transistors (MOSFET) on silicon, germanium, GaAs , etc. still demands the creation of new high-k dielectrics with even better material performance. In this research, a new ternary high-k dielectric film, LaSmO3 , is deposited using electron-beam evaporation. The structure and high temperature interfacial thermal stabilities are investigated by X-ray diffraction (XRD), X-ray photon electronic spectra (XPS), infrared attenuated total reflection (ATR) and time of flight second ion mass spectroscopy (ToF-SIMS). The band gap and band offset are determined using the O 1s energy loss spectra and valence band difference between film and substrate, respectively, from the XPS spectra. Capacitance-voltage (CV) and current-voltage (IV) curves are measured to give an insight of the dielectric and leakage current of this material. It is found that crystallization temperature of LaSmO3 is >1000°C. The high dielectric constant (k) = 24.6, large band gap (Eg) > 7 eV and low leakage current (1.8 × 10-4 A/cm2, 1 MV/cm) make LaSmO3 to be a promising high-k candidate.

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