IMPLEMENTATION OF THE SLIDING MEDIAN METHOD ON FPGA FOR SENSOR SIGNALS PRE-PROCESSING

The use of modern hardware platforms in the development of computer system components, including digital signal processing, allows to describe circuit solutions using specialized languages such as AlteraHDL, VHDL, Verilog, etc. One of the options for using the resources of programmable logic integrated circuits is to create digital components of signal pre-processing, in particular in information and measurement channels. The application of this approach is due to the presence of various distortions that lead to information and accuracy loss. Another problem is the need to preserve the information performance of such information and measurement channels. It is common to use analog implementations of signal pre-processing methods, in particular different types filters. In this case, the implementation of pre-processing methods at the hardware level will provide the appropriate processing speed at insignificant hardware costs. The paper proposes the implementation of the algorithm for processing information and measurement signals using the sliding median method, implemented on a programmable logic integrated circuit. Based on the simulation in a numerical experiment, the efficiency of using such a method is shown in a relatively simple implementation scheme on the FPGA platform. In fact, the pyramidal scheme of conditional constructions provides a simple description of the logical scheme by means of the Altera HDL language, and also allows to reduce the number of comparison operations. The proposed algorithm does not require complex hardware resources, which allows you to effectively involve typical circuit solutions.