scholarly journals RANCANGAN RANGKAIAN ANTI BOUNCING UNTUK RANGKAIAN DIGITAL

Sutet ◽  
2018 ◽  
Vol 7 (1) ◽  
pp. 24-31
Author(s):  
Redaksi Tim Jurnal
Keyword(s):  
Electric Current ◽  
Input Signal ◽  
Input Data ◽  
Digital Circuits ◽  
Electronic Circuit ◽  
Digital Electronics ◽  
Mechanical Contacts ◽  
Mechanical Switch

Push-On switches or toggle switches and mechanical relays are mechanical contacts made of metal which, when supplied with electric current, will result in a spike of electrical sparks, called Bouncing Effects. Bounce effects are often a problem in digital circuits, especially in digital electronics circuits, because these Bounce Effects will cause the value of data or signals coming into the circuit inaccurate or indeterminate, when the mechanical switch is pressed as input data. This will undoubtedly lead to undesirable conditions and must be overcome with an electronic circuit called De-Bounce for the data or input signal to be more certain.

Analysis and comparison of fast multiplier circuits based on different parameters

2018 ◽  
Vol 7 (3) ◽  
pp. 1189
Author(s):  
Mr Aaron D’costa ◽  
Dr Abdul Razak ◽  
Dr Shazia Hasan
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Electronic Circuit ◽  
Vlsi Circuit ◽  
Silicon Area ◽  
Lower Power ◽  
Digital Electronics ◽  
Design Specifications ◽  
Important Design ◽  
Multiplier Circuit

Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.  

SIMILARITY OF OUTPUT TRACES AS A SEISMIC OPERATOR CRITERION

Geophysics ◽  
1955 ◽  
Vol 20 (2) ◽  
pp. 254-269 ◽  
Author(s):  
Stephen M. Simpson
Keyword(s):  
Input Signal ◽  
Input Data ◽  
Signal To Noise Ratio ◽  
Linear Operators ◽  
High Input ◽  
Signal To Noise ◽  
Numerical Work ◽  
Input And Output ◽  
Definition Of

The problem of emphasizing signals on multiple trace seismograms is approached by considering a relationship between the input and output records. It is proposed that the transformation to output record be one which causes the output traces to be most “similar” or “in phase” according to a certain definition of this property. If the noise and signal are “properly behaved,” it may be demonstrated that a linear transformation chosen by this criterion must have a response emphasizing frequency ranges of high input signal‐to‐noise ratio. The determination of such a transformation from the input data alone is carried out for discrete linear operators. The numerical work involved in computing such operators is formidable. As an example the computations were carried out for a mixture of an artificial signal introduced into a noise record. The results are about as good as those obtained with conventional filtering techniques depending on prior knowledge of input signal‐to‐noise ratios.

scholarly journals Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

2021 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Narendra Kumar Garg ◽  
Vivek Singh Kushwah ◽  
Manisha Pattanaik
Keyword(s):  
Digital Circuits ◽  
Leakage Power ◽  
Performance Parameters ◽  
New Techniques ◽  
Vlsi Interconnects ◽  
Digital Electronics ◽  
Spice Model ◽  
On Chip ◽  
Carbon Nano Tube ◽  
The Impact

Abstract With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.

scholarly journals Simulator Arsitektural Dari Sirkuit Elektronis Guna Tujuan Pembelajaran

Faktor Exacta ◽  
2018 ◽  
Vol 11 (3) ◽  
Author(s):  
Suryo Bramasto ◽  
Sunarto Sunarto
Keyword(s):  
Process Model ◽  
Digital Circuits ◽  
Electronic Circuit ◽  
Circuit Simulation ◽  
Object Oriented Programming ◽  
Cycle Basis ◽  
Circuit Simulator ◽  
Analog And Digital Circuits ◽  
Visualization And Simulation ◽  
Architectural Simulation

<p align="justify">The electronic circuit engineering learning processes generally requires specific infrastructures which sometimes constrained to cost factors in the procurement. Circuit simulator could be an alternative as electronic circuit engineering learning tool. Architectural simulation provides designers the ability to quickly examine a wide variety of design choices. The recent trend in system design toward architectures that react to circuit-level phenomena has outstripped the capabilities of traditional cycle-based architectural simulators. In this paper, a simulator that incorporates a circuit modeling capability, permitting architectural-level simulations that react to circuit characteristics (such as latency, energy, power brightness, or current draw) on a cycle-by-cycle basis is presented. As for learning purpose, circuit template and pre-built circuits for many categories are provided. The environment enables process visualization and simulation of analog and digital circuits. The system enables the creation of many laboratory exercises, which offer students opportunities to follow visually characteristic processes in analog and digital circuits. At this research, Rational Unified Process (RUP) software process model and Object Oriented Programming (OOP) are implemented.<br />Keywords: architectural simulation, circuit simulation, learning, RUP, OOP</p>

scholarly journals Checkability of the circuits in FPGA designs according to power dissipation

2019 ◽  
pp. 3-9
Author(s):  
V. V. Antoniuk ◽  
A. V. Drozd ◽  
J. V. Drozd ◽  
H. S. Stepova
Keyword(s):  
Power Dissipation ◽  
Input Data ◽  
Digital Circuits ◽  
Short Circuit ◽  
Logical Form ◽  
Dual Mode ◽  
Fpga Chip ◽  
Analytical Assessment ◽  
Short Circuits ◽  
Emergency Mode

The authors consider the checkability issues of FPGA designs and analyze the logical (structural and structurally functional) checkability. The paper describes the features of safety-related systems that can operate in normal and emergency mode. In these modes different input data are fed to the inputs of the digital circuits of the components, which leads to an expansion of the structurally functional checkability to dual-mode. The paper shows the problem of hidden faults, which can accumulate in the normal mode and manifest themselves in the emergency mode. The features of checkability of circuits in FPGA projects and its advantages important for critical applications are noted. The limitations of the logical checkability of the circuits are analyzed, as well as the possibility and expediency of expanding the traditionally used logical form to power usage checkability. The study defines the checkability of circuits in FPGA projects by power usage and determines its subtypes — lower and upper checkability. Lower checkability is important in identifying faults that lead to lower power usage, for example, in chains of common signals, such as reset or synchronization. The upper one is important for identifying faults that increase the level of power usage, for example, short-circuits. The authors identify the possibility of assessing the power usage checkability of FPGA projects in terms of the power dissipation or power consumption and indicate the possibility of developing upper checkability by the dissipated power. The features of power dissipation monitoring for FPGA projects are noted. An analytical assessment for the checkability of circuits for short-circuit faults, which increase the dissipated power, and the organization of monitoring its excess are proposed. Experiments in Quartus Prime Lite CAD to assess upper checkability by power dissipation of scalable shift register circuits, that are implemented in FPGA projects, based on default IP-Core and a custom VHDL description, are carried out. The paper presents experimental results, that estimate the dependence of the checkability level on the area, occupied by the circuit on the FPGA chip.

scholarly journals Prominent Speed Low Power Compressor Based Multiplier for Proficient VLSI Architecture

2020 ◽  
pp. 228-232
Author(s):  
V. Supraja ◽  
S. Sandhya ◽  
Y. Lavanya ◽  
M. Bhavana ◽  
V. Keerthana
Keyword(s):  
Low Power ◽  
Significant Role ◽  
Electronic Circuit ◽  
Vlsi Architecture ◽  
Computation Time ◽  
Cmos Technology ◽  
Operating Modes ◽  
Digital Electronics ◽  
Almost All

In the recent years the computational units are optimized to reduce the computation time. Multiplier is an electronic circuit used in digital electronics and has a significant role in vlsi applications. The 4:2 compressors have a flexibility of switching between exact and appropriate operating modes. In the appropriate mode the dual quality compressors provides higher speeds and consumes low power. Using these compressors in the structures of parallel multipliers provides configurable multipliers whose accuracies (as well as their powers and speeds) may change dynamically during the runtime. The efficiencies of these compressors are used in another type of multiplier and are evaluated in 45 nm standard CMOS technology. By comparing the parameters of this multiplier with those of appropriate multipliers, the results indicate a better in almost all the aspects.

scholarly journals A Digital Device for Automatic Checking of Homework Assignments in the Digital Circuits Course

2020 ◽  
Vol 35 ◽  
pp. 04009
Author(s):  
Sergey I. Gavrilenkov ◽  
Elizaveta O. Petrenko ◽  
Evgeny V. Arbuzov
Keyword(s):  
Digital Circuits ◽  
Logic Gates ◽  
Digital Circuit ◽  
Education Quality ◽  
Output Variable ◽  
Digital Device ◽  
Digital Electronics ◽  
Logical Expression ◽  
Manual Testing ◽  
Truth Tables

This paper considers a digital device for automatic checking of homework assignments in the digital circuits course. The assignment is to make a digital circuit corresponding to a given logical expression; the circuit is comprised of elementary logic gates. The process of manual testing the built circuit is very labor-intensive because checking a circuit with N inputs variables requires checking the correctness of the output variable for 2N cases. We propose automating this pro-cess with a special digital device. The device is comprised of a microcontroller connected to the circuit tested. The microcontroller is connected to a personal computer with an application written in C# for executing the main operations of the testing process. During testing, the student chooses from a database or enters the logical expression corresponding to the circuit tested. For the expression, the software generates truth tables where actual and required responses of the circuit are given. Actual circuit responses are acquired by probing the circuit via the microcontroller, and the expected values are calculated from the logical expression. The truth tables are then presented to the student with a message of whether the circuit works correctly or not. The device was integrated into the process of checking homework assignments in the digital electronics course, and it significantly sped up the process of checking homework assignment circuits, resulting in better education quality.

scholarly journals CREST project focused on neuromorphic devices and networks

Impact ◽  
2020 ◽  
Vol 2020 (5) ◽  
pp. 6-9
Author(s):  
Isao H Inoue
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Big Data ◽  
Input Data ◽  
Electronic Circuit ◽  
Statistical Processing ◽  
Low Power Consumption ◽  
The Neural Network ◽  
Artificial Neurons ◽  
Neuromorphic Architecture

The artificial neural network is a type of electronic circuit modelled after the human brain. It contains thousands of artificial neurons and synapses that, in general, assemble to execute algorithms that can allow the neural network to incorporate a large amount of input data. One of the algorithms is known as deep learnig (DL), which is a kind of statistical processing to learn and infer several features of the big data while consuming tremendous energy. A team, led by Dr Isao H Inoue of the National Institute of Advanced Industrial Science and Technology (AIST), is working on a five-and-a-half-year CREST project until March 2025 to develop a novel neuromorphic architecture that can do the learning and inference without using such an algorithm, thus in low power consumption.

scholarly journals Novel Characterizations of the JK Bistables (Flip Flops)

2019 ◽  
pp. 1-20
Author(s):  
Ali Muhammad Ali Rushdi ◽  
Fares Ahmad Muhammad Ghaleb
Keyword(s):  
Present State ◽  
Digital Circuits ◽  
State Table ◽  
Flip Flop ◽  
Digital Electronics ◽  
Equation Solving ◽  
Analysis And Synthesis ◽  
Boolean Equation ◽  
Control Circuits ◽  
And Control

The JK flip flop is a flexible type of bistable elements that has extensive uses in digital electronics and control circuits. It is usually described by its characteristic equation or next-state table (used for analysis purposes) and its excitation table (used for synthesis purposes). This paper explores a variety of novel characterizations of JK flip flops. First, equational and implicational descriptions are presented, and methods of logic deduction are utilized to produce complete statements of all propositions that are true for a general JK flip flop. Next, methods of Boolean-equation solving are employed to find all possible ways to express the excitations in terms of the present state and next state. The concept of Boolean quotient is used to impose certain requirements so as to find particularly useful expressions of the excitations. Relations of JK flip flops to other types of flip flops are also explored. This paper is expected to provide an immediate pedagogical benefit, and to help facilitate the analysis and synthesis of sequential digital circuits.

scholarly journals An Information-Theoretic Perspective on Proper Quaternion Variational Autoencoders

Entropy ◽  
2021 ◽  
Vol 23 (7) ◽  
pp. 856
Author(s):  
Eleonora Grassucci ◽  
Danilo Comminiello ◽  
Aurelio Uncini
Keyword(s):  
Input Signal ◽  
Input Data ◽  
Generative Models ◽  
Second Order ◽  
Audio Signals ◽  
Information Theoretic ◽  
Input Distribution ◽  
Latent Space ◽  
Latent Distribution ◽  
Quaternion Signals

Variational autoencoders are deep generative models that have recently received a great deal of attention due to their ability to model the latent distribution of any kind of input such as images and audio signals, among others. A novel variational autoncoder in the quaternion domain H, namely the QVAE, has been recently proposed, leveraging the augmented second order statics of H-proper signals. In this paper, we analyze the QVAE under an information-theoretic perspective, studying the ability of the H-proper model to approximate improper distributions as well as the built-in H-proper ones and the loss of entropy due to the improperness of the input signal. We conduct experiments on a substantial set of quaternion signals, for each of which the QVAE shows the ability of modelling the input distribution, while learning the improperness and increasing the entropy of the latent space. The proposed analysis will prove that proper QVAEs can be employed with a good approximation even when the quaternion input data are improper.

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