scholarly journals An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1768
Author(s):  
Changho Hyun ◽  
Yong-Un Jeong ◽  
Suhwan Kim ◽  
Joo-Hyung Chae
Keyword(s):  
Energy Efficiency ◽  
Output Signal ◽  
Impedance Matching ◽  
Active Area ◽  
Cmos Process ◽  
Output Level ◽  
Code Generator ◽  
Code Table ◽  
Output Driver

This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. The ZQ code generator then adaptively selected the appropriate codes depending on the data pattern and delivered them to the output driver; this can improve the level separation mismatch ratio (RLM) while matching the channel impedance. To validate the effectiveness of our approach, a prototype chip with an active area of 0.035 mm2 was fabricated in a 65 nm CMOS process. It achieved the energy efficiency of 3.09 pJ/bit/pin at 18 Gb/s/pin, and its RLM was 0.971 while matching the channel impedance.

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

scholarly journals A Reconfigurable Radio-Frequency Converter IC in 0.18 µm CMOS

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1146
Author(s):  
Carlos Sánchez-Azqueta ◽  
Erick Guerrero ◽  
Cecilia Gimeno ◽  
Santiago Celma
Keyword(s):  
Wavelength Division Multiplexing ◽  
Frequency Synthesizer ◽  
Frequency Converter ◽  
Impedance Matching ◽  
Cmos Process ◽  
Wavelength Division ◽  
Triple Play ◽  
Band Pass ◽  
Reconfigurable Radio ◽  
Lc Tank

This work presents a reconfigurable RF converter for DVB-T television applications using triple-play over GPON. The system takes the DVB-T input, a wavelength division multiplexing (WDM) signal with spectral inversion in the range from 47 M Hz –1000 M Hz , up-converts its frequency to the band-pass of a highly selective surface-acoustic wave (SAW) filter centered at 1 . 3 G Hz , and then down-converts it so that it is compatible with the antenna input of conventional television sets. The designed RF converter incorporates two pairs of frequency synthesizer and mixer, based, respectively, on an integer-N phase-locked loop (PLL) with two LC-tank VCOs with 128 coarse tuning bands in the range from 1.35 G Hz –2.7 G Hz , and a double-balanced Gilbert cell, modified for better impedance matching and improved linearity. It is fed with regulated supplies compensated in temperature and programmed by an I 2 C interface operating on five 16-bit registers. This work presents the experimental characterization of the whole system plus selected cells for stand-alone testing, which have been fabricated in a 0 . 18 m CMOS process.

Research and Analysis of Tunable Differential N-Path Band-Pass Filter

2020 ◽  
pp. 2150055
Author(s):  
Shuxiang Song ◽  
Guolun Liu ◽  
Mingcan Cen ◽  
Chaobo Cai
Keyword(s):  
Bandpass Filter ◽  
Noise Figure ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Transmission Function ◽  
Center Frequency ◽  
Cmos Process ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Circuit Structure

Traditional filters usually have low Q and gain values and it is difficult to adjust their center frequencies. Moreover, it is very complicated to analyze their transmission charateristics through conventional methods. Therefore, in this paper, a tunable differential N-path bandpass filter that uses a new adjoint network method to analyze the transmission characteristics of the differential N-path structure is proposed. The filter circuit adopts a novel circuit structure consisting of two differential N-path structures, two transconductance amplifiers and an off-chip transformer. The differential structure eliminates even harmonics, the transconductance amplifier increases the circuit gain and the off-chip transformer acts as a balun, improving the filter’s Q value and achieving impedance matching. Unlike the traditional switching capacitance method used for analyzing the differential circuit structure, the method proposed in this paper does not involve complicated calculus operations. In fact, the method greatly simplifies these complex operations, and the transmission function of the circuit can be obtained through simple algebraic operations. The proposed filter was designed using TSMC 180[Formula: see text]nm CMOS process. Simulation results for a differential four-path bandpass filter formed under 1.2[Formula: see text]V supply voltage show that the gain of the filter is greater than 8.5 dB, the center frequency can be adjusted from 0.1[Formula: see text]GHz to 1[Formula: see text]GHz, the in-band insertion loss S11 is greater than 10 dB, the out-of-band IIP3 is greater than 10 dBm, the out-of-band rejection is 28 dB and the noise figure is less than 2.2 dB at [Formula: see text][Formula: see text]MHz.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

2020 ◽  
pp. 2150136
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Input Matching ◽  
Inductive Peaking ◽  
Linearity Improvement ◽  
Noise Amplifier ◽  
Path Structure

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

2021 ◽  
pp. 11-20
Author(s):  
Nguyen Huu Tho
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Wide Band ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Wide Range ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier

This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third-order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2.

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

A Dual Band RF Energy Harvester with Hybrid Threshold Voltage Self-Compensation

2016 ◽  
Vol 25 (06) ◽  
pp. 1650055 ◽  
Author(s):  
Lianxi Liu ◽  
Wenzhi Yuan ◽  
Junchao Mu ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Threshold Voltage ◽  
Energy Harvester ◽  
Impedance Matching ◽  
Forward Bias ◽  
Input Power ◽  
Dual Band ◽  
Maximum Efficiency ◽  
Cmos Process ◽  
Rf Energy ◽  
Rf Energy Harvester

Threshold voltage self-compensation technology (TVSC) has been widely used in RF energy harvester. In this paper, the influence of the size of rectifying transistors, the stages and compensation orders of the rectifier, and the impedance matching network on the performance of RF energy harvester has been studied. A dual band RF energy harvester with hybrid threshold voltage self-compensation (HTVSC) is proposed in this paper in 65-nm CMOS process according to the distribution characteristic of the ambient RF energy. By combining TVSC and the technology of weak forward bias between the source and body of the rectifying transistor, the threshold voltage of MOSFET can be dramatically decreased. The performance of the RF energy harvester has been improved using this new technology. The simulation results show that the proposed dual band RF energy harvester can acquire energy at the band of 900[Formula: see text]MHz and 2.4[Formula: see text]GHz. At 900[Formula: see text]MHz-band (825–960[Formula: see text]MHz), with 1[Formula: see text]M[Formula: see text] load resistor, the output voltage of the energy harvester can be over 1.0[Formula: see text]V with a minimum [Formula: see text]18[Formula: see text]dBm RF input power and a maximum 13.8% power conversion efficiency (PCE). At 2.4[Formula: see text]GHz-band (2.4–2.485[Formula: see text]GHz), the minimum input power can be as low as [Formula: see text]19[Formula: see text]dBm with a maximum efficiency of 16.8%.

Scotch

2020 ◽  
Vol 14 (3) ◽  
pp. 281-293
Author(s):  
Martin Kiefer ◽  
Ilias Poulakis ◽  
Sebastian Breß ◽  
Volker Markl
Keyword(s):  
Energy Efficiency ◽  
Large Scale ◽  
Broad Class ◽  
Approximate Query Processing ◽  
Code Generator ◽  
Domain Specific ◽  
Large Scale Network ◽  
Hardware Description ◽  
Definition Of ◽  
High Level

Sketching algorithms are a powerful tool for single-pass data summarization. Their numerous applications include approximate query processing, machine learning, and large-scale network monitoring. In the presence of high-bandwidth interconnects or in-memory data, the throughput of summary maintenance over input data becomes the bottleneck. While FPGAs have shown admirable throughput and energy-efficiency for data processing tasks, developing FPGA accelerators requires a sophisticated hardware design and expensive manual tuning by an expert. We propose Scotch, a novel system for accelerating sketch maintenance using FPGAs. Scotch provides a domain-specific language for the user-friendly, high-level definition of a broad class of sketching algorithms. A code generator performs the heavy-lifting of hardware description, while an auto-tuning algorithm optimizes the summary size. Our evaluation shows that FPGA accelerators generated by Scotch outperform CPU- and GPU-based sketching by up to two orders of magnitude in terms of throughput and up to a factor of five in terms of energy efficiency.

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