An Ultra-Low-Power CMOS Supercapacitor Storage Unit for Energy Harvesting Applications

This work presents an ultra-low-power CMOS supercapacitor storage unit suitable for a plethora of low-power autonomous applications. The proposed unit exploits the unregulated voltage output of harvesting circuits (i.e., DC-DC converters) and redirects the power to the storage elements and the working loads. Being able to adapt to the input energy conditions and the connected loads' supply demands offers extended survival to the system with the self-startup operation and voltage regulation. A low-complexity control unit is implemented which is composed of power switches, comparators and logic gates and is able to supervise two supercapacitors, a small and a larger one, as well as a backup battery. Two separate power outputs are offered for external load connection which can be controlled by a separate unit (e.g., microcontroller). Furthermore, user-controlled parameters such as charging and discharging supercapacitor voltage thresholds, provide increased versatility to the system. The storage unit was designed and fabricated in a 0.18 um standard CMOS process and operates with ultra-low current consumption of 432 nA at 2.3 V. The experimental results validate the proper operation of the overall structure.

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Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols

IACR Transactions on Cryptographic Hardware and Embedded Systems ◽

10.46586/tches.v2019.i4.17-61 ◽

2019 ◽

pp. 17-61 ◽

Cited By ~ 5

Author(s):

Utsav Banerjee ◽

Tenzin S. Ukyab ◽

Anantha P. Chandrakasan

Keyword(s):

Low Power ◽

Large Scale ◽

Energy Savings ◽

Logic Gates ◽

Public Key Cryptography ◽

Building Blocks ◽

Modular Arithmetic ◽

Cmos Process ◽

Order Of Magnitude ◽

Low Power Cmos

Public key cryptography protocols, such as RSA and elliptic curve cryptography, will be rendered insecure by Shor’s algorithm when large-scale quantum computers are built. Cryptographers are working on quantum-resistant algorithms, and lattice-based cryptography has emerged as a prime candidate. However, high computational complexity of these algorithms makes it challenging to implement lattice-based protocols on low-power embedded devices. To address this challenge, we present Sapphire – a lattice cryptography processor with configurable parameters. Efficient sampling, with a SHA-3-based PRNG, provides two orders of magnitude energy savings; a single-port RAM-based number theoretic transform memory architecture is proposed, which provides 124k-gate area savings; while a low-power modular arithmetic unit accelerates polynomial computations. Our test chip was fabricated in TSMC 40nm low-power CMOS process, with the Sapphire cryptographic core occupying 0.28 mm2 area consisting of 106k logic gates and 40.25 KB SRAM. Sapphire can be programmed with custom instructions for polynomial arithmetic and sampling, and it is coupled with a low-power RISC-V micro-processor to demonstrate NIST Round 2 lattice-based CCA-secure key encapsulation and signature protocols Frodo, NewHope, qTESLA, CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order of magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations. All key building blocks of Sapphire are constant-time and secure against timing and simple power analysis side-channel attacks. We also discuss how masking-based DPA countermeasures can be implemented on the Sapphire core without any changes to the hardware.

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Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology

2017 European Conference on Circuit Theory and Design (ECCTD) ◽

10.1109/ecctd.2017.8093232 ◽

2017 ◽

Author(s):

Marten Vohrmann ◽

Philippe Geisler ◽

Thorsten Jungeblut ◽

Ulrich Ruckert

Keyword(s):

Low Power ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Logic Gates ◽

Ultra Low Power ◽

Low Power Cmos ◽

Soi Technology ◽

28 Nm

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Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v4.i3.pp213-218 ◽

2015 ◽

Vol 4 (3) ◽

pp. 213

Author(s):

Vandana Shukla ◽

O. P. Singh ◽

G. R. Mishra ◽

R. K. Tiwari

Keyword(s):

Low Power ◽

Optical Computing ◽

Logic Gates ◽

Reversible Logic ◽

Optimized Design ◽

Storage Unit ◽

Computing Device ◽

Cmos Design ◽

Low Power Cmos ◽

Logic Approach

Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.

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An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽

10.3390/electronics10080889 ◽

2021 ◽

Vol 10 (8) ◽

pp. 889

Author(s):

Xiaoying Deng ◽

Peiqi Tan

Keyword(s):

Power Consumption ◽

Low Power ◽

Tuning Range ◽

Frequency Tuning ◽

Cmos Process ◽

Voltage Controlled Oscillator ◽

Back Gate ◽

Ultra Low Power ◽

Current Reuse ◽

K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽

10.3390/electronics10070805 ◽

2021 ◽

Vol 10 (7) ◽

pp. 805

Author(s):

Shi Zuo ◽

Jianzhong Zhao ◽

Yumei Zhou

Keyword(s):

Low Power ◽

Current Efficiency ◽

Phase Noise ◽

Duty Cycle ◽

Semiconductor Manufacturing ◽

Figure Of Merit ◽

Room Temperature ◽

Cmos Process ◽

Ultra Low Power ◽

Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

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A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11020019 ◽

2021 ◽

Vol 11 (2) ◽

pp. 19

Author(s):

Francesco Centurelli ◽

Riccardo Della Sala ◽

Pietro Monsurrò ◽

Giuseppe Scotti ◽

Alessandro Trifiletti

Keyword(s):

Low Power ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Process ◽

Slew Rate ◽

Large Signal ◽

Output Stage ◽

Ultra Low Power ◽

Input Stage ◽

Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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