Process dependence and nucleus models of β-Sn grains in SAC305 freestanding solder balls and BGA solder joints

Author(s):  
X.L. Ren ◽  
Y.P. Wang ◽  
X.Y. Liu ◽  
L.J. Zou ◽  
N. Zhao
Keyword(s):  
2019 ◽  
Vol 16 (2) ◽  
pp. 91-102
Author(s):  
Lars Bruno ◽  
Benny Gustafson

Abstract Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.


2019 ◽  
Vol 6 (10) ◽  
pp. 106302 ◽  
Author(s):  
Yufeng Jiao ◽  
Kittisak Jermsittiparsert ◽  
Aleksandr Yu Krasnopevtsev ◽  
Qahtan A Yousif ◽  
Mohammad Salmani

Author(s):  
Yong Liu ◽  
Howard Allen ◽  
Stephen Martin

This paper presents a power stack die package design for a point of load buck converter. The buck converter system in package (SiP) consists of a lower side Mosfet and a high side Mosfet together with an IC controller. Its structure includes a premolded leadframe with an IC controller. The two Mosfets (both low side and higher side) are stacked on the premolded leadfrrame (LF) and IC controller. Solder balls are placed on the leadframe’s exposed lands, and together with the two drains of Mosfets, to form the stacked die power package. The thermal cycling simulations for the solder balls to connect the PCB and solder joints of the two Mosfet die to the leadframe pads are studied. The failure mechanism and reliability analysis of the power package in TMCL test are discussed.


2004 ◽  
Vol 127 (4) ◽  
pp. 430-439 ◽  
Author(s):  
Ahmad Abu Obaid ◽  
Jay G. Sloan ◽  
Mark A. Lamontia ◽  
Antonio Paesano ◽  
Subhotosh Khan ◽  
...  

The objective of this work was to experimentally determine the in situ creep behavior and constitutive model equations for a commercial area array package and printed wiring board assembly at −40, 23, and 125 °C through shear loading. The chip is connected to the printed circuit board by means of solder joints made of 62%Sn–36%Pb–2%Ag alloy. It was shown that the creep rate of solder ball arrays could be investigated using a stress relaxation method. Under the shear relaxation mode, the creep strain increases with temperature and can be described by a power law model with coefficients determined by finite element modeling (FEM). An analytical model was developed to describe the stress relaxation of an array with an arbitrary number of solder balls by defining an equivalent solder ball shear area as a fitting parameter. The resulting constitutive model is in excellent agreement with both FEM and experimental results at all test temperatures. A parametric study is conducted to investigate the creep response as a function of temperature for arrays consisting of a wide range of solder balls.


2010 ◽  
Vol 25 (9) ◽  
pp. 1854-1858 ◽  
Author(s):  
S.H. Kim ◽  
Jin Yu

In this investigation on the formation of multiple-layered Kirkendall voids at Cu/Sn–3.5Ag solder joints, Sn–3.5Ag solder balls were reacted with Cu under bump metallurgy (UBM), which was electroplated using bis-sodium sulfopropyl–disulfide, C6H12O6S4Na2 (SPS) additive. The sequence of multilayer Kirkendall voids and Cu–Sn IMC (intermetallic compounds) formations are explained with the aid of cross-sectional scanning electron microscopy (SEM) micrographs and schematic diagrams. During the aging treatment at 150 °C, layers of Cu6Sn5/Cu3Sn formed at the solder joints and Kirkendall voids nucleated at the Cu3Sn/Cu interface as a result of the segregation of residual S originating from SPS. However, with Kirkendall void growth, the net section area of the Cu/Cu3Sn interface decreased and the Cu flux into Cu3Sn was inhibited. As the atomic ratio of Cu against Sn in the Cu3Sn dropped, transformation of Cu3Sn into Cu6Sn5 ensued. Subsequent diffusion of Sn atoms into the remaining Cu UBM through the remaining ligament of the Cu6Sn5/Cu interface precipitated secondary Cu3Sn beneath the primary Cu3Sn/Cu interface, and the secondary Kirkendall voids formed at the new Cu3Sn/Cu interface and so on.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000409-000417 ◽  
Author(s):  
Natalja Schafet ◽  
Bruno Schrempp ◽  
Manfred Spraul ◽  
Ulrich Becker ◽  
Herbert Güttler

PBGAs with SnPb and SnAgCu (SAC) solder joints were stressed with temperature cycles on board- and system-level. A significant influence of the different solder materials on the location of the most damaged PBGA solder balls was observed in the experiment. The reason for this experimental finding was investigated and explained by FE–simulation. The simulations of the PBGAs were done on package-, board- and system-level (PCB within a metal housing). For the system level simulation a 2-step sub-model technique described in [1] was used. Through such an approach the transient PCB deformation and the transient temperature field within the ECU-housing can be incorporated into a creep simulation of the PBGA solder joints. The creep results for both SnPb and SnAgCu solder joints from the board- and system-level simulation were compared. The calculated damage factor due to the ECU-housing influence is different for PBGA with SnPb and SAC solder joints. The simulation results were validated step by step with measurements and experiments: warpage of the non-soldered PBGA, mechanical strain and temperature on the mounted PCB, crack length evaluation of all PBGA solder joints.


2006 ◽  
Vol 46 (8) ◽  
pp. 1335-1347 ◽  
Author(s):  
T. Kangasvieri ◽  
O. Nousiainen ◽  
J. Putaala ◽  
R. Rautioaho ◽  
J. Vähäkangas

2000 ◽  
Vol 15 (8) ◽  
pp. 1679-1687 ◽  
Author(s):  
J. W. Jang ◽  
C. Y. Liu ◽  
P. G. Kim ◽  
K. N. Tu ◽  
A. K. Mal ◽  
...  

We examined the interfacial morphology and shear deformation of flip chip solder joints on an organic substrate (chip-on-board). The large differences in the coefficients of thermal expansion between the board and the chip resulted in bending of the 1-cm2 chip with a curvature of 57 ± 12 cm. The corner bump pads on the chip registered a relative misalignment of 10 μm with respect to those on the board, resulting in shear deformation of the solder joints. The mechanical properties of these solder joints were tested on samples made by sandwiching two Si chips with electroless Ni(P) as the under-bump metallization and 25 solder interconnects. Joints were sheared to failure. Fracture was found to occur along the solder/Ni3Sn4 interface. In addition, cracking and peeling damages of the SiO2 dielectric layer were observed in the layer around the solder balls, indicating that damage to the dielectric layer may have occurred prior to the fracture of the solder joints due to a large normal stress. The failure behavior of the solder joints is characterized by an approximate stress analysis.


2018 ◽  
Vol 30 (2) ◽  
pp. 87-99 ◽  
Author(s):  
Barbara Dziurdzia ◽  
Maciej Sobolewski ◽  
Janusz Mikolajek

Purpose The aim of this paper is to evaluate using statistical methods how two soldering techniques – the convection reflow and vapour phase reflow with vacuum – influence reduction of voids in lead-free solder joints under Light Emitted Diodes (LEDs) and Ball Grid Arrays (BGAs). Design/methodology/approach Distribution of voids in solder joints under thermal and electrical pads of LEDs and in solder balls of BGAs assembled with convection reflow and vapour phase reflow with vacuum has been investigated in terms of coverage or void contents, void diameters and number of voids. For each soldering technology, 80 LEDs and 32 solder balls in BGAs were examined. Soldering processes were carried out in the industrial or semi-industrial environment. The OM340 solder paste of Innolot type was used for LED soldering. Voidings in solder joints were inspected with a 2D X-ray transmission system. OriginLab was used for statistical analysis. Findings Investigations supported by statistical analysis showed that the vapour phase reflow with vacuum decreases significantly void contents and number and diameters of voids in solder joints under LED and BGA packages when compared to convection reflow. Originality/value Voiding distribution data were collected on the basis of 2D X-ray images for test samples manufactured during the mass production processes. Statistical analysis enabled to appraise soldering technologies used in these processes in respect of void formation.


2020 ◽  
Vol 17 (1) ◽  
pp. 13-22
Author(s):  
Simon Schambeck ◽  
Matthias Hutter ◽  
Johannes Jaeschke ◽  
Andrea Deutinger ◽  
Martin Schneider-Ramelow

Abstract The combination of continuous miniaturization of electronics and the demanding reliability requirements for industrial and automotive electronics is one big challenge for emerging packaging technology. One aspect is to increase the understanding of the damage under environmental loading. Therefore, the solder joints of a wafer-level chip-scale package assembled on a printed circuit board (PCB) have been analyzed after a temperature cycling test. In the case of the investigated package, a limited number of joints did not form a proper mechanical connection with the PCB copper pad. Although not intended in the first place, these circumstances cause a detachment of those joints within the first few thermal cycles. However, this constellation offers a unique opportunity to compare the solder joint microstructure after thermomechanical loading (connected joints) with pure thermal loading (detached joints) located directly next to each other. It is shown that microstructure aging effects can be directly linked to regions in the joint with increased loading. This is particularly the case for detached joints, which could almost retain their initial microstructure up to the effect of the high-temperature part of the thermal profile. By means of finite element simulation, it is further possible to quantify the increased loading on adjacent joints if isolated solder balls detach from the board. In one case presented, the lifetime of the corner joint was calculated to reduce up to 85% only.


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