High performance wafer level underfill material with high filler loading

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

Download Full-text

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2017dpc-tp2_presentation3 ◽

2017 ◽

Vol 2017 (DPC) ◽

pp. 1-19

Author(s):

Raquel Pinto ◽

André Cardoso ◽

Sara Ribeiro ◽

Carlos Brandão ◽

João Gaspar ◽

...

Keyword(s):

Structural Material ◽

High Performance ◽

Microelectromechanical Systems ◽

Low Cost ◽

Process Conditions ◽

Processing Temperature ◽

Wafer Level ◽

Fast Growing ◽

Wide Range ◽

Different Types

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

Download Full-text

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

International Symposium on Microelectronics ◽

10.4071/isom-wp11 ◽

2014 ◽

Vol 2014 (1) ◽

pp. 000599-000605 ◽

Cited By ~ 13

Author(s):

Woon-Seong Kwon ◽

Suresh Ramalingam ◽

Xin Wu ◽

Liam Madden ◽

C. Y. Huang ◽

...

Keyword(s):

High Performance ◽

Process Integration ◽

Cost Effective ◽

Disruptive Innovation ◽

Design Rule ◽

Wind Condition ◽

Silicon Etching ◽

Wafer Level ◽

Effective Manner ◽

Interconnect Technology

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Download Full-text

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.452 ◽

2015 ◽

Vol 12 (3) ◽

pp. 111-117

Author(s):

Woon-Seong Kwon ◽

Suresh Ramalingam ◽

Xin Wu ◽

Liam Madden ◽

C. Y. Huang ◽

...

Keyword(s):

High Performance ◽

Flip Chip ◽

Process Integration ◽

Cost Effective ◽

Design Rule ◽

Innovative Technology ◽

Wind Condition ◽

Wafer Level ◽

Effective Manner ◽

Interconnect Technology

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Download Full-text

A High Q-Factor Outer-Frame-Anchor Gyroscope Operating at First Resonant Mode

Micromachines ◽

10.3390/mi11121071 ◽

2020 ◽

Vol 11 (12) ◽

pp. 1071

Author(s):

Bo Jiang ◽

Yan Su ◽

Guowen Liu ◽

Lemin Zhang ◽

Fumin Liu

Keyword(s):

High Performance ◽

Microelectromechanical Systems ◽

Resonant Mode ◽

Low Noise ◽

Silicon On Insulator ◽

Q Factor ◽

Wafer Level ◽

High Q ◽

Ring Structures ◽

Static Performance

Disc gyroscope manufactured through microelectromechanical systems (MEMS) fabrication processes becomes one of the most critical solutions for achieving high performance. Some reported novel disc constructions acquire good performance in bias instability, scale factor nonlinearity, etc. However, antivibration characteristics are also important for the devices, especially in engineering applications. For multi-ring structures with central anchors, the out-of-plane motions are in the first few modes, easily excited within the vibration environment. The paper presents a multi-ring gyro with good dynamic characteristics, operating at the first resonant mode. The design helps obtain better static performance and antivibration characteristics with anchor points outside of the multi-ring resonator. According to harmonic experiments, the nearest interference mode is located at 30,311 Hz, whose frequency difference is 72.8% far away from working modes. The structures were fabricated with silicon on insulator (SOI) processes and wafer-level vacuum packaging, where the asymmetry is 780 ppm as the frequency splits. The gyro also obtains a high Q-factor. The measured value at 0.15 Pa was 162 k, which makes the structure have sizeable mechanical sensitivity and low noise.

Download Full-text

Residual Stress in Silicon Caused by Cu-Sn Wafer-Level Packaging

Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes ◽

10.1115/ipack2013-73317 ◽

2013 ◽

Author(s):

Maaike M. V. Taklo ◽

Astrid-Sofie Vardøy ◽

Ingrid De Wolf ◽

Veerle Simons ◽

H. J. van de Wiel ◽

...

Keyword(s):

Residual Stress ◽

Integrated Circuit ◽

High Performance ◽

White Light Interferometry ◽

Wafer Level ◽

Noticeable Effect ◽

Micro Raman Spectroscopy ◽

Wafer Level Packaging ◽

Mems Device ◽

Specific Technology

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

Download Full-text