Power dissipation and interconnect noise challenges in nanometer CMOS technologies

2010 ◽  
Vol 29 (3) ◽  
pp. 26-31 ◽  
Author(s):  
Ndubuisi Ekekwe
2010 ◽  
Vol 29-32 ◽  
pp. 1930-1936 ◽  
Author(s):  
Jian Ping Hu ◽  
Li Fang Ye ◽  
Li Su

Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing total leakage dissipations with additional load capacitances using SPICE simulations. Compared to N-type clocked adiabatic logic (N-CAL) circuits, the total power and leakage power dissipation of P-type CAL circuits are reduced greatly.


2010 ◽  
Vol 121-122 ◽  
pp. 97-102 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Li Su ◽  
Li Fang Ye ◽  
Jian Ping Hu

The leakage dissipations of nano-circuits have become a critical concern. Estimating the leakage power of nano-circuits is very important in low-power design. This paper presents a new estimation technology for the active leakage dissipations of adiabatic logic circuits. Based on the power dissipation models of adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations with additional capacitances on load nodes of the adiabatic circuits using HSPICE simulations. Taken as an example, the estimation for dynamic and active leakage power dissipations of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits is demonstrated using the proposed estimation technology. The simulation results show that the proposed estimation technology can accurately estimate the active leakage dissipations of CPAL circuits with an accepted error over a wide range of frequencies.


2010 ◽  
Vol E93-C (12) ◽  
pp. 1670-1678 ◽  
Author(s):  
Ehsan ESFANDIARI ◽  
Norman Bin MARIUN ◽  
Mohammad Hamiruce MARHABAN ◽  
Azmi ZAKARIA

2014 ◽  
Vol 4 (3) ◽  
pp. 9-13
Author(s):  
M. Balaji ◽  
◽  
B. Keerthana ◽  
K. Varun ◽  
◽  
...  

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.


Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.


Materials ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2456
Author(s):  
Zhijun Yang ◽  
Weixin Yu ◽  
Shaoting Lang ◽  
Junyi Wei ◽  
Guanglong Wang ◽  
...  

The hot deformation behaviors of a new Ti-6Al-2Nb-2Zr-0.4B titanium alloy in the strain rate range 0.01–10.0 s−1 and temperature range 850–1060 °C were evaluated using hot compressing testing on a Gleeble-3800 simulator at 60% of deformation degree. The flow stress characteristics of the alloy were analyzed according to the true stress–strain curve. The constitutive equation was established to describe the change of deformation temperature and flow stress with strain rate. The thermal deformation activation energy Q was equal to 551.7 kJ/mol. The constitutive equation was ε ˙=e54.41[sinh (0.01σ)]2.35exp(−551.7/RT). On the basis of the dynamic material model and the instability criterion, the processing maps were established at the strain of 0.5. The experimental results revealed that in the (α + β) region deformation, the power dissipation rate reached 53% in the range of 0.01–0.05 s−1 and temperature range of 920–980 °C, and the deformation mechanism was dynamic recovery. In the β region deformation, the power dissipation rate reached 48% in the range of 0.01–0.1 s−1 and temperature range of 1010–1040 °C, and the deformation mechanism involved dynamic recovery and dynamic recrystallization.


2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.


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