Impact of Thermal Sub-Continuum Effects on Electrical Performance of Silicon-on-Insulator Transistors

In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. Effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated into a electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of gate length and silicon layer thickness. The device thermal resistance is increased by nearly a factor of 3 due to the scaling of gate length from 180nm to 10nm. Self-heating in SOI devices with gate length of 10nm can be responsible for up to 30% reduction in the saturation current and neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two.

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Effect of Illumination on Organic Polymer Thin-Film Transistors

MRS Proceedings ◽

10.1557/proc-771-l10.17 ◽

2003 ◽

Vol 771 ◽

Cited By ~ 3

Author(s):

Michael C. Hamilton ◽

Sandrine Martin ◽

Jerzy Kanicki

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Drain Current ◽

Charge Carriers ◽

Electrical Performance ◽

Organic Polymer ◽

Light Illumination ◽

Polymer Thin Film ◽

Channel Region ◽

White Light Illumination

AbstractWe have investigated the effects of white-light illumination on the electrical performance of organic polymer thin-film transistors (OP-TFTs). The OFF-state drain current is significantly increased, while the drain current in the strong accumulation regime is relatively unaffected. At the same time, the threshold voltage is decreased and the subthreshold slope is increased, while the field-effect mobility of the charge carriers is not affected. The observed effects are explained in terms of the photogeneration of free charge carriers in the channel region due to the absorbed photons.

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High Temperature Endurance of Packaged SOI Devices for Signal Conditioning and Processing Applications

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/hiten-paper8-sriches ◽

2011 ◽

Vol 2011 (HITEN) ◽

pp. 000251-000254

Author(s):

S T Riches ◽

C Johnston ◽

M Sousa ◽

P Grant

Keyword(s):

High Temperature ◽

Electronic Materials ◽

Silicon On Insulator ◽

Electrical Performance ◽

Research Centre ◽

Signal Conditioning ◽

Reliability Data ◽

Die Attach ◽

Soi Devices ◽

Formed Part

Silicon on Insulator (SOI) device technology is fulfilling a niche requirement for electronics that functions satisfactorily at operating temperatures of >200°C. Most of the reliability data on the high temperature endurance of the devices is generated on the device itself with little attention being paid to the packaging technology around the device. Similarly, most of the reliability data generated on high temperature packaging technologies uses testpieces rather than real devices, which restricts any conclusions on long term electrical performance. This paper presents results of high temperature endurance studies on SOI devices combined with high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. The endurance studies have been carried out for up to 7,056 hours at 250°C, with functioning devices being tested periodically at room temperature, 125°C and 250°C. Different die attach and wire bond options have been included in the study and the performance of multiplexers, transistors, bandgap voltage, oscillators and voltage regulators functional blocks have been characterised. This work formed part of the UPTEMP project which was set-up with support from UK Technology Strategy Board and the EPSRC. The project brought together a consortium of end-users (Sondex Wireline and Vibro-Meter UK), electronic module manufacturers (GE Aviation Systems Newmarket) and material suppliers (Gwent Electronic Materials and Thermastrate Ltd) with Oxford University-Materials Department, the leading UK high temperature electronics research centre.

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Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors

Electronics ◽

10.3390/electronics8050538 ◽

2019 ◽

Vol 8 (5) ◽

pp. 538

Author(s):

Farhad Larki ◽

Md Shabiul Islam ◽

Arash Dehzangi ◽

Mohammad Tariqul Islam ◽

Hin Yong Wong

Keyword(s):

Computer Aided Design ◽

Three Dimensional ◽

Drain Current ◽

Channel Length ◽

Influential Factors ◽

Gate Length ◽

Current Characteristics ◽

Lateral Gate ◽

The Impact ◽

Gate Design

In this paper, we investigate the effect of lateral gate design on performance of a p-type double lateral gate junctionless transistors (DGJLTs) with an air gate gap. The impact of lateral gate length, which modifies the real channel length of the device and gate gap variation down to 50 nm which have been found to be the most influential factors in the performance of the device have been comprehensively investigated. The characteristics are demonstrated and compared with a nominal DGJLTs through three-dimensional technology computer-aided design (TCAD) simulation. At constant channel geometry (thickness and width), when the lateral gate length decreases, the results show constant flatband drain current characteristics while the OFF state current (IOFF) increases significantly. On the other hand, by decreasing the air gap the subthreshold current considerably decreases while the flatband current is constant. Moreover, at a certain gate gap, the gates lose control over the channel and the device simply works as a resistor. Electric field component, carriers’ density, band edge energies, and recombination rate of the carriers inside the channel in depletion and accumulation regimes are analysed to interpret the variation of output characteristics.

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Output Conductance of Line-TFETs for Different Device Parameters and its Effect on Basic Analog Circuits

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v15i1.112 ◽

2020 ◽

Vol 15 (1) ◽

pp. 1-7 ◽

Cited By ~ 1

Author(s):

Walter Gonçalez Filho ◽

João Antonio Martino ◽

Paula Ghedini Der Agopian

Keyword(s):

Analog Circuits ◽

Analog Circuit ◽

Field Effect Transistors ◽

Drain Current ◽

Common Source ◽

Gate Length ◽

Current Mirrors ◽

Conduction Mechanisms ◽

The Impact ◽

Output Conductance

This work addresses the impact of different device parameters on the analog characteristics of Line-Tunneling Field Effect Transistors (Line-TFETs). Source-to-drain separation, pocket thickness, pocket doping, gate-source alignment and the gate length are varied in order to evaluate their impact on the conduction mechanisms and on the overall transfer characteristics of the device. The variation of the main parameters responsible for device variability (pocket thickness and doping and gate-source alignment) is performed in order to analyze their impact on current mirrors, revealing that gate-source overlap improves the analog characteristics of the Line-TFET and that pocket doping should be limited to values smaller than 1018cm-3. Even though the drain current and the transconductance (gm) of this device are proportional to the gate area, simulations compared to experimental data show that the output conductance (gd) of Line-TFETs is practically independent of the gate length. The conduction mechanisms were analyzed through numerical simulations, revealing that this unique characteristic is due to source-to-drain tunneling, which defines the average value of gd on the saturation-like region and does not depend upon the gate length. The impact of this characteristic on analog circuit design is illustrated considering the example of a common-source stage and comparing its design when using MOSFET devices. This example reveals that the designer may choose whether to increase gm or gd in order to increase the circuit gain when using Line-TFETs, fundamentally differing from the MOSFET design.

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Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v14i2.34 ◽

2019 ◽

Vol 14 (2) ◽

pp. 1-8

Author(s):

Egon Henrique Salerno Galembeck ◽

Denis Flandre ◽

Christian Renaux ◽

Salvador Pinillos Gimenez

Keyword(s):

High Temperature ◽

Field Effect Transistors ◽

Drain Current ◽

Cmos Technology ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Electrical Performance ◽

Soi Mosfet ◽

Temperature Conditions ◽

Channel Lengths

This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

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MONTE-CARLO SIMULATION OF ULTRA-THIN FILM SILICON-ON-INSULATOR MOSFETs

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156413500018 ◽

2013 ◽

Vol 22 (01) ◽

pp. 1350001

Author(s):

FRANCISCO GÁMIZ ◽

CARLOS SAMPEDRO ◽

LUCA DONETTI ◽

ANDRES GODOY

Keyword(s):

Monte Carlo ◽

Ground Plane ◽

Silicon On Insulator ◽

Slab Thickness ◽

Short Channel ◽

Fully Depleted ◽

Ensemble Monte Carlo ◽

Soi Devices ◽

Monte Carlo Simulator ◽

The Impact

State-of-the-Art devices are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Ultrathin fully depleted Silicon-on-Insulator transistors and multi-gate devices based on SOI technology are the best candidates to become a standard solution to overcome the problems arising from such aggressive scaling. Moreover, the flexibility of SOI wafers and processes allows the use of different channel materials, substrate orientations and layer thicknesses to enhance the performance of CMOS circuits. From the point of view of simulation, these devices pose a significant challenge. Simulations tools have to include quantum effects in the whole structure to correctly describe the behavior of these devices. The Multi-Subband Monte Carlo (MSB-MC) approach constitutes today's most accurate method for the study of nanodevices with important applications to SOI devices. After reviewing the main basis of MSB-MC method, we have applied it to answer important questions which remain open regarding ultimate SOI devices. In the first part of the chapter we present a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin fully depleted SOI devices using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX+GP) solutions have been considered in order to check their influence on short channel effects (SCEs). The simulations show that the main limiting factor for downscaling is the DIBL and the UTBOX+GP configuration is the only valid one to downscale SGSOI transistors beyond 20 nm channel length keeping the silicon slab thickness above the theoretical limit of 5 nm, where thickness variability and mobility reduction would play an important role. In the second part, we have used the multisubband Ensemble Monte Carlo simulator to study the electron transport in ultrashort DGSOI devices with different confinement and transport directions. Our simulation results show that transport effective mass, and subband redistribution are the main factors that affect drift and scattering processes and, therefore, the general performance of DGSOI devices when orientation is changed

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Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v9i4.pp2863-2873 ◽

2019 ◽

Vol 9 (4) ◽

pp. 2863

Author(s):

K. E. Kaharudin ◽

F. Salehuddin ◽

A. S. M. Zain ◽

Ameer F. Roslan

Keyword(s):

Process Design ◽

Concentration Level ◽

Drain Current ◽

Channel Length ◽

Electrical Performance ◽

Double Gate ◽

Electrical Characteristics ◽

Metal Gate ◽

The Impact ◽

Gate Work Function

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

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Voiding and Thermal Resistance Modeling and Characterization for a QFN Assembly

Volume 4: Electronics and Photonics ◽

10.1115/imece2010-38391 ◽

2010 ◽

Cited By ~ 1

Author(s):

Harish Gadepalli ◽

Rangaraj Dhanasekaran ◽

S. Manian Ramkumar ◽

Tim Jensen ◽

Ed Briggs

Keyword(s):

Thermal Resistance ◽

Void Formation ◽

Primary Objective ◽

Void Volume ◽

Thermal Dissipation ◽

Electrical Performance ◽

Solder Paste ◽

Resistance Response ◽

Response Variable ◽

The Impact

Quad Flatpack No lead (QFN) packages have become a popular choice in electronics packaging due to its small form factor. They are also gaining rapid industry acceptance because of its excellent thermal and electrical performance. The bottom side of the QFN package has a large thermal pad. This exposed die attach pad effectively conducts heat to the PCB and also provides a stable ground connection. Effective soldering of this surface to the pad on the PCB is required for good thermal dissipation and component functionality. The exposed thermal pad presents various challenges during the surface mount assembly process. One major challenge is solder void formation. Voids are primarily formed due to the entrapment of volatiles in flux outgassing during the reflow process. The primary objective of this study is to determine optimal parameters to minimize void formation in QFN packages (QFN16, QFN20, QFN28, QFN32 and QFN44), specifically the reflow profile, lead-free solder paste and stencil aperture opening for the thermal pad. A systematic Design of Experiments (DOE) based approach was used to arrive at conclusions, using the ratio of void volume on the thermal pad to the actual volume of solder paste printed, as the response variable. A theoretical thermal resistance response variable was also modeled to analyze the DOE parameters and the conclusions were similar to the void model. Various graphs are presented to understand the impact of different parameters. Interaction graphs are used to determine optimal settings for each parameter. A regression equation for relationship between the factors and the void volume is identified to predict void volumes for any given component, paste volume and paste transfer efficiency.

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MODELING OF DEEP-SUBMICRON MOSFET DRIVE CURRENT

International Journal of Nanoscience ◽

10.1142/s0219581x05003243 ◽

2005 ◽

Vol 04 (04) ◽

pp. 525-536

Author(s):

BENISTANT FRANCIS

Keyword(s):

Electric Field ◽

Drain Current ◽

Critical Issue ◽

Deep Submicron ◽

Gate Length ◽

Actual Performance ◽

Back Scattering ◽

Clear Link ◽

Carrier Velocity ◽

The Impact

With already published MOSFET transistors of 25 nm gate length, the limit of the available current is a critical issue which must be clarified in order to guide the optimization of the transistor architecture. Leburton and Dorda1 showed that the limitation of the drain current comes from the saturation of the electric field at the source, and not from the saturation of the carrier velocity. More recently, Lundstrom2 compared the actual performance of the deep-sub-micron devices with their ballistic limit, and showed that the back-scattering at the source end of the channel is responsible for the limitation of the drain current. In both studies, the electric field, at the source end of the channel, plays a key part on the performances of the transistor. In this paper, we will review quantitatively this limitation, and, in addition, we are going to give a clear link between the drain current equations given by Lundstorm and the usual classical ones. Finally, we will examine the impact of the overshoot velocity on the transistor behavior.

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